diff options
Diffstat (limited to 'tests/configs/realview-simple-timing.py')
| -rw-r--r-- | tests/configs/realview-simple-timing.py | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py index b5db3e10b..28cd3163f 100644 --- a/tests/configs/realview-simple-timing.py +++ b/tests/configs/realview-simple-timing.py @@ -37,8 +37,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -78,7 +78,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave |