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-rw-r--r--tests/configs/simple-atomic-mp-ruby.py11
1 files changed, 8 insertions, 3 deletions
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 12c26d97b..9feccb12c 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -38,13 +38,18 @@ import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
-system.clock = '1GHz'
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
+ clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
# add L1 caches
for cpu in cpus:
cpu.connectAllPorts(system.membus)
- cpu.clock = '2GHz'
+ # All cpus are associated with cpu_clk_domain
+ cpu.clk_domain = system.cpu_clk_domain
# connect memory to membus
system.physmem.port = system.membus.master