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-rw-r--r--tests/configs/simple-atomic-mp.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index 966ae24fe..0324bcc04 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -50,7 +50,7 @@ system.l2c.mem_side = system.membus.slave
# add L1 caches
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
- L1Caches(size = '32kB', assoc = 4))
+ L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache