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Diffstat (limited to 'tests/configs/simple-timing-mp.py')
| -rw-r--r-- | tests/configs/simple-timing-mp.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 7a8da70bb..f5793b282 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -71,7 +71,7 @@ for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache - cpu.connectMemPorts(system.toL2Bus) + cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.clock = '2GHz' # connect memory to membus |