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Diffstat (limited to 'tests/configs/simple-timing-mp.py')
| -rw-r--r-- | tests/configs/simple-timing-mp.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 5ec7a6067..f898797bb 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -70,6 +70,8 @@ system.l2c.mem_side = system.membus.slave for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4)) + # create the interrupt controller + cpu.createInterruptController() # connect cpu level-1 caches to shared level-2 cache cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.clock = '2GHz' |