diff options
Diffstat (limited to 'tests/configs/simple-timing-mp.py')
-rw-r--r-- | tests/configs/simple-timing-mp.py | 32 |
1 files changed, 5 insertions, 27 deletions
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 3e5e92d8c..aad15a2ac 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -28,30 +28,8 @@ import m5 from m5.objects import * - -# -------------------- -# Base L1 Cache -# ==================== - -class L1(BaseCache): - hit_latency = 2 - response_latency = 2 - block_size = 64 - mshrs = 4 - tgts_per_mshr = 8 - is_top_level = True - -# ---------------------- -# Base L2 Cache -# ---------------------- - -class L2(BaseCache): - block_size = 64 - hit_latency = 20 - response_latency = 20 - mshrs = 92 - tgts_per_mshr = 16 - write_buffers = 8 +m5.util.addToPath('../configs/common') +from Caches import * nb_cores = 4 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] @@ -61,7 +39,7 @@ system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) # l2cache & bus system.toL2Bus = CoherentBus(clock = '2GHz') -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus @@ -69,8 +47,8 @@ system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: - cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller cpu.createInterruptController() # connect cpu level-1 caches to shared level-2 cache |