diff options
Diffstat (limited to 'tests/configs/simple-timing-mp.py')
| -rw-r--r-- | tests/configs/simple-timing-mp.py | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 559cf807a..3e5e92d8c 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -34,8 +34,8 @@ from m5.objects import * # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -47,8 +47,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -60,8 +60,8 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) # l2cache & bus -system.toL2Bus = CoherentBus() -system.l2c = L2(size='4MB', assoc=8) +system.toL2Bus = CoherentBus(clock = '2GHz') +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus |