diff options
Diffstat (limited to 'tests/configs/simple-timing-ruby.py')
| -rw-r--r-- | tests/configs/simple-timing-ruby.py | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index ce155c23c..df8fdf2be 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -67,19 +67,24 @@ options.l3_assoc=2 options.num_cpus = 1 cpu = TimingSimpleCPU(cpu_id=0) -system = System(cpu = cpu, physmem = SimpleMemory(null = True), - clk_domain = SrcClockDomain(clock = '1GHz')) +system = System(cpu = cpu, physmem = SimpleMemory(null = True)) +# Dummy voltage domain for all our clock domains +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) +system.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = system.voltage_domain) # Create a seperate clock domain for components that should run at # CPUs frequency -system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') +system.cpu.clk_domain = SrcClockDomain(clock = '2GHz', + voltage_domain = system.voltage_domain) system.mem_ranges = AddrRange('256MB') Ruby.create_system(options, system) # Create a separate clock for Ruby -system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) assert(len(system.ruby._cpu_ruby_ports) == 1) |