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Diffstat (limited to 'tests/configs/simple-timing.py')
| -rw-r--r-- | tests/configs/simple-timing.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 5269f4127..33d03f6cf 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -45,7 +45,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), MyCache(size = '2MB', latency='10ns')) system = System(cpu = cpu, physmem = SimpleMemory(), - membus = Bus()) + membus = CoherentBus()) system.system_port = system.membus.slave system.physmem.port = system.membus.master # create the interrupt controller |