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-rw-r--r--tests/configs/simple-timing.py20
1 files changed, 5 insertions, 15 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index beeadced9..5a851ba25 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -28,23 +28,13 @@
import m5
from m5.objects import *
-
-class MyCache(BaseCache):
- assoc = 2
- block_size = 64
- hit_latency = 2
- response_latency = 2
- mshrs = 10
- tgts_per_mshr = 5
-
-class MyL1Cache(MyCache):
- is_top_level = True
+m5.util.addToPath('../configs/common')
+from Caches import *
cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
- MyL1Cache(size = '256kB'),
- MyCache(size = '2MB', hit_latency= 20,
- response_latency = 20))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
+ L1Cache(size = '256kB'),
+ L2Cache(size = '2MB'))
system = System(cpu = cpu,
physmem = SimpleMemory(),
membus = CoherentBus())