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Diffstat (limited to 'tests/configs/simple-timing.py')
| -rw-r--r-- | tests/configs/simple-timing.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index b366f01e5..046ee96dd 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -39,6 +39,7 @@ system = System(cpu = cpu, physmem = SimpleMemory(), membus = CoherentBus(), mem_mode = "timing") +system.clock = '1GHz' system.system_port = system.membus.slave system.physmem.port = system.membus.master # create the interrupt controller |