summaryrefslogtreecommitdiff
path: root/tests/configs/simple-timing.py
diff options
context:
space:
mode:
Diffstat (limited to 'tests/configs/simple-timing.py')
-rw-r--r--tests/configs/simple-timing.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index d7d505a5a..6c4b8232f 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -44,5 +44,6 @@ system = System(cpu = cpu,
membus = Bus())
system.physmem.port = system.membus.port
cpu.connectMemPorts(system.membus)
+cpu.clock = '2GHz'
root = Root(system = system)