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Diffstat (limited to 'tests/configs/simple-timing.py')
| -rw-r--r-- | tests/configs/simple-timing.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 5a851ba25..b366f01e5 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -37,7 +37,8 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), L2Cache(size = '2MB')) system = System(cpu = cpu, physmem = SimpleMemory(), - membus = CoherentBus()) + membus = CoherentBus(), + mem_mode = "timing") system.system_port = system.membus.slave system.physmem.port = system.membus.master # create the interrupt controller |