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-rw-r--r--tests/configs/simple-timing.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index cc0d1d207..19b40fe48 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -51,4 +51,4 @@ system.physmem.port = system.membus.port
cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
-root = Root(system = system)
+root = Root(full_system=False, system = system)