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Diffstat (limited to 'tests/configs/simple-timing.py')
| -rw-r--r-- | tests/configs/simple-timing.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index ea9428d8a..cd6bee863 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -48,6 +48,8 @@ system = System(cpu = cpu, membus = Bus()) system.system_port = system.membus.slave system.physmem.port = system.membus.master +# create the interrupt controller +cpu.createInterruptController() cpu.connectAllPorts(system.membus) cpu.clock = '2GHz' |