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-rw-r--r--tests/configs/simple-timing.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 19b40fe48..ea9428d8a 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -46,8 +46,8 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
-system.system_port = system.membus.port
-system.physmem.port = system.membus.port
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'