diff options
Diffstat (limited to 'tests/configs/tsunami-o3-dual.py')
| -rw-r--r-- | tests/configs/tsunami-o3-dual.py | 51 |
1 files changed, 14 insertions, 37 deletions
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index 9aac5e744..d7964b4d8 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -1,6 +1,15 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited # All rights reserved. # +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright @@ -24,42 +33,10 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Authors: Steve Reinhardt +# Authors: Andreas Sandberg -import m5 from m5.objects import * -m5.util.addToPath('../configs/common') -import FSConfig -from Caches import * - -#cpu -cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ] -#the system -system = FSConfig.makeLinuxAlphaSystem('timing') - -system.cpu = cpus -#create the l1/l2 bus -system.toL2Bus = CoherentBus(clock = '2GHz') -system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')]) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave - - -#connect up the l2 cache -system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave - -#connect up the cpu and l1s -for c in cpus: - c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), - L1Cache(size = '32kB', assoc = 4)) - # create the interrupt controller - c.createInterruptController() - # connect cpu level-1 caches to shared level-2 cache - c.connectAllPorts(system.toL2Bus, system.membus) - c.clock = '2GHz' - -root = Root(full_system=True, system=system) -m5.ticks.setGlobalFrequency('1THz') +from alpha_generic import * +root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=DerivO3CPU, + num_cpus=2).create_root() |