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-rw-r--r--tests/configs/tsunami-simple-atomic-dual.py43
1 files changed, 40 insertions, 3 deletions
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 7ed854f44..131095055 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -31,12 +31,49 @@ from m5.objects import *
m5.AddToPath('../configs/common')
import FSConfig
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ protocol = CoherenceProtocol(protocol='moesi')
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+#cpu
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
+#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
+
system.cpu = cpus
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
for c in cpus:
- c.connectMemPorts(system.membus)
+ c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+ # connect cpu level-1 caches to shared level-2 cache
+ c.connectMemPorts(system.toL2Bus)
+ c.clock = '2GHz'
root = Root(system=system)
-
-m5.ticks.setGlobalFrequency('2GHz')
+m5.ticks.setGlobalFrequency('1THz')