diff options
Diffstat (limited to 'tests/configs/twosys-tsunami-simple-atomic.py')
| -rw-r--r-- | tests/configs/twosys-tsunami-simple-atomic.py | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py index b69e35517..e84a06aaf 100644 --- a/tests/configs/twosys-tsunami-simple-atomic.py +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -35,8 +35,12 @@ from Benchmarks import * test_sys = makeLinuxAlphaSystem('atomic', SysConfig('netperf-stream-client.rcS')) +# Dummy voltage domain for all test_sys clock domains +test_sys.voltage_domain = VoltageDomain() + # Create the system clock domain -test_sys.clk_domain = SrcClockDomain(clock = '1GHz') +test_sys.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = test_sys.voltage_domain) test_sys.cpu = AtomicSimpleCPU(cpu_id=0) # create the interrupt controller @@ -45,10 +49,14 @@ test_sys.cpu.connectAllPorts(test_sys.membus) # Create a seperate clock domain for components that should run at # CPUs frequency -test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz') +test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz', + voltage_domain = + test_sys.voltage_domain) # Create a separate clock domain for Ethernet -test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz') +test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', + voltage_domain = + test_sys.voltage_domain) # In contrast to the other (one-system) Tsunami configurations we do # not have an IO cache but instead rely on an IO bridge for accesses @@ -62,8 +70,12 @@ test_sys.physmem.port = test_sys.membus.master drive_sys = makeLinuxAlphaSystem('atomic', SysConfig('netperf-server.rcS')) +# Dummy voltage domain for all drive_sys clock domains +drive_sys.voltage_domain = VoltageDomain() # Create the system clock domain -drive_sys.clk_domain = SrcClockDomain(clock = '1GHz') +drive_sys.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = + drive_sys.voltage_domain) drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) # create the interrupt controller drive_sys.cpu.createInterruptController() @@ -71,10 +83,14 @@ drive_sys.cpu.connectAllPorts(drive_sys.membus) # Create a seperate clock domain for components that should run at # CPUs frequency -drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz') +drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz', + voltage_domain = + drive_sys.voltage_domain) # Create a separate clock domain for Ethernet -drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz') +drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', + voltage_domain = + drive_sys.voltage_domain) drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges) drive_sys.iobridge.slave = drive_sys.iobus.master |