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-rw-r--r--tests/configs/twosys-tsunami-simple-atomic.py6
1 files changed, 2 insertions, 4 deletions
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index 84f70db14..d0c90e135 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -41,8 +41,7 @@ test_sys.cpu.connectAllPorts(test_sys.membus)
# In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses
# from masters on the IO bus to the memory bus
-test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
- ranges = [AddrRange(0, '8GB')])
+test_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')])
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
@@ -52,8 +51,7 @@ drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
-drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
- ranges = [AddrRange(0, '8GB')])
+drive_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')])
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave