8 files changed, 48 insertions, 10 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 004424af5..00a668a7b 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -34,9 +34,12 @@ from m5.objects import *
 nb_cores = 8
 cpus = [ MemTest() for i in xrange(nb_cores) ]
 
+import ruby_config
+ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
+
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = RubyMemory(num_cpus=nb_cores),
+                physmem = ruby_memory,
                 membus = Bus(clock="500GHz", width=16))
 
 for cpu in cpus:
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index b9aade84e..eab9bfaf2 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -33,9 +33,11 @@ m5.AddToPath('../configs/common')
 nb_cores = 4
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
 
+import ruby_config
+ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
+
 # system simulated
-system = System(cpu = cpus, physmem = RubyMemory(num_cpus=nb_cores),
-                membus = Bus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
 
 for cpu in cpus:
     cpu.connectMemPorts(system.membus)
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 394550987..a91a9cf39 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -31,11 +31,14 @@ from m5.objects import *
 m5.AddToPath('../configs/common')
 
 
+import ruby_config
+ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1)
+
 cpu = DerivO3CPU(cpu_id=0)
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
-                physmem = RubyMemory(),
+                physmem = ruby_memory,
                 membus = Bus())
 system.physmem.port = system.membus.port
 cpu.connectMemPorts(system.membus)
diff --git a/tests/configs/ruby_config.py b/tests/configs/ruby_config.py
new file mode 100644
index 000000000..7b8e27613
--- /dev/null
+++ b/tests/configs/ruby_config.py
@@ -0,0 +1,20 @@
+import os
+import subprocess
+
+from os.path import dirname, join as joinpath
+
+import m5
+
+def generate(config_file, cores=1, memories=1, memory_size=1024):
+    default = joinpath(dirname(__file__), '../../src/mem/ruby/config')
+    ruby_config = os.environ.get('RUBY_CONFIG', default)
+    args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"),
+             "-r", joinpath(ruby_config, config_file), "-p", str(cores),
+             "-m", str(memories), "-s", str(memory_size)]
+
+    temp_config = joinpath(m5.options.outdir, "ruby.config")
+    ret = subprocess.call(args, stdout=file(temp_config, "w"))
+    if ret != 0:
+        raise RuntimeError, "subprocess failed!"
+
+    return m5.objects.RubyMemory(config_file=temp_config, num_cpus=cores)
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index c03ede9b1..1b60418d0 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -33,9 +33,11 @@ from m5.objects import *
 nb_cores = 4
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
+import ruby_config
+ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
+
 # system simulated
-system = System(cpu = cpus, physmem = RubyMemory(num_cpus=nb_cores),
-                membus = Bus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
 
 # add L1 caches
 for cpu in cpus:
diff --git a/tests/configs/simple-atomic-ruby.py b/tests/configs/simple-atomic-ruby.py
index 95f922ddc..c9c61788c 100644
--- a/tests/configs/simple-atomic-ruby.py
+++ b/tests/configs/simple-atomic-ruby.py
@@ -29,8 +29,11 @@
 import m5
 from m5.objects import *
 
+import ruby_config
+ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1)
+
 system = System(cpu = AtomicSimpleCPU(cpu_id=0),
-                physmem = RubyMemory(),
+                physmem = ruby_memory,
                 membus = Bus())
 system.physmem.port = system.membus.port
 system.cpu.connectMemPorts(system.membus)
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index df019c321..ed4b5b4c6 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -32,9 +32,11 @@ from m5.objects import *
 nb_cores = 4
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
+import ruby_config
+ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
+
 # system simulated
-system = System(cpu = cpus, physmem = RubyMemory(num_cpus=nb_cores),
-                membus = Bus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
 
 # add L1 caches
 for cpu in cpus:
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index b921e4812..d3cd7273f 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -29,9 +29,12 @@
 import m5
 from m5.objects import *
 
+import ruby_config
+ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1)
+
 cpu = TimingSimpleCPU(cpu_id=0)
 system = System(cpu = cpu,
-                physmem = RubyMemory(),
+                physmem = ruby_memory,
                 membus = Bus())
 system.physmem.port = system.membus.port
 cpu.connectMemPorts(system.membus)