diff options
Diffstat (limited to 'tests/configs')
-rw-r--r-- | tests/configs/base_config.py | 30 | ||||
-rw-r--r-- | tests/configs/memtest-ruby.py | 17 | ||||
-rw-r--r-- | tests/configs/memtest.py | 17 | ||||
-rw-r--r-- | tests/configs/o3-timing-mp-ruby.py | 11 | ||||
-rw-r--r-- | tests/configs/o3-timing-ruby.py | 10 | ||||
-rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 8 | ||||
-rw-r--r-- | tests/configs/rubytest-ruby.py | 7 | ||||
-rw-r--r-- | tests/configs/simple-atomic-mp-ruby.py | 11 | ||||
-rw-r--r-- | tests/configs/simple-timing-mp-ruby.py | 11 | ||||
-rw-r--r-- | tests/configs/simple-timing-ruby.py | 11 | ||||
-rw-r--r-- | tests/configs/tgen-simple-dram.py | 4 | ||||
-rw-r--r-- | tests/configs/tgen-simple-mem.py | 4 | ||||
-rw-r--r-- | tests/configs/twosys-tsunami-simple-atomic.py | 26 |
13 files changed, 125 insertions, 42 deletions
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index 0cafacdda..16620c4dd 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -74,9 +74,10 @@ class BaseSystem(object): self.num_cpus = num_cpus self.checker = checker - def create_cpus(self): + def create_cpus(self, cpu_clk_domain): """Return a list of CPU objects to add to a system.""" - cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') + cpus = [ self.cpu_class(clk_domain = cpu_clk_domain, + cpu_id=i) for i in range(self.num_cpus) ] if self.checker: for c in cpus: @@ -101,8 +102,9 @@ class BaseSystem(object): Returns: A bus that CPUs should use to connect to the shared cache. """ - system.toL2Bus = CoherentBus(clock='2GHz') - system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8) + system.toL2Bus = CoherentBus(clk_domain=system.cpu_clk_domain) + system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, + size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave return system.toL2Bus @@ -134,8 +136,8 @@ class BaseSystem(object): Arguments: system -- System to initialize. """ - system.clock = '1GHz' - system.cpu = self.create_cpus() + self.create_clk_src(system) + system.cpu = self.create_cpus(system.cpu_clk_domain) if _have_kvm_support and \ any([isinstance(c, BaseKvmCPU) for c in system.cpu]): @@ -145,6 +147,16 @@ class BaseSystem(object): for cpu in system.cpu: self.init_cpu(system, cpu, sha_bus) + def create_clk_src(self,system): + # Create system clock domain. This provides clock value to every + # clocked object that lies beneath it unless explicitly overwritten + # by a different clock domain. + system.clk_domain = SrcClockDomain(clock = '1GHz') + + # Create a seperate clock domain for components that should + # run at CPUs frequency + system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') + @abstractmethod def create_system(self): """Create an return an initialized system.""" @@ -244,8 +256,10 @@ class BaseFSSwitcheroo(BaseFSSystem): BaseFSSystem.__init__(self, **kwargs) self.cpu_classes = tuple(cpu_classes) - def create_cpus(self): - cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True) + def create_cpus(self, cpu_clk_domain): + cpus = [ cclass(clk_domain = cpu_clk_domain, + cpu_id=0, + switched_out=True) for cclass in self.cpu_classes ] cpus[0].switched_out = False return cpus diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index dbd1082d1..3261ba3ff 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -69,7 +69,7 @@ options.l3_assoc=2 nb_cores = 8 # ruby does not support atomic, functional, or uncacheable accesses -cpus = [ MemTest(clock = '2GHz', atomic=False, percent_functional=50, +cpus = [ MemTest(atomic=False, percent_functional=50, percent_uncacheable=0, suppress_func_warnings=True) \ for i in xrange(nb_cores) ] @@ -80,11 +80,22 @@ options.num_cpus = nb_cores system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), physmem = SimpleMemory(null = True), - funcbus = NoncoherentBus()) -system.clock = options.sys_clock + funcbus = NoncoherentBus(), + clk_domain = SrcClockDomain(clock = options.sys_clock)) + +# Create a seperate clock domain for components that should run at +# CPUs frequency +system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') + +# All cpus are associated with cpu_clk_domain +for cpu in cpus: + cpu.clk_domain = system.cpu_clk_domain Ruby.create_system(options, system) +# Create a separate clock domain for Ruby +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) + assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index efaae6133..35efe646d 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -33,18 +33,21 @@ from Caches import * #MAX CORES IS 8 with the fals sharing method nb_cores = 8 -cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ] +cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), funcbus = NoncoherentBus(), physmem = SimpleMemory(), - membus = CoherentBus(width=16)) -system.clock = '1GHz' + membus = CoherentBus(width=16), + clk_domain = SrcClockDomain(clock = '1GHz')) -# l2cache & bus -system.toL2Bus = CoherentBus(clock="2GHz", width=16) -system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8) +# Create a seperate clock domain for components that should run at +# CPUs frequency +system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') + +system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16) +system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus @@ -52,6 +55,8 @@ system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: + # All cpus are associated with cpu_clk_domain + cpu.clk_domain = system.cpu_clk_domain cpu.l1c = L1Cache(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.test cpu.l1c.mem_side = system.toL2Bus.slave diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py index 0060689b8..292c7a42d 100644 --- a/tests/configs/o3-timing-mp-ruby.py +++ b/tests/configs/o3-timing-mp-ruby.py @@ -39,14 +39,19 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) # system simulated system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(), - mem_mode = "timing") -system.clock = '1GHz' + mem_mode = "timing", + clk_domain = SrcClockDomain(clock = '1GHz')) + +# Create a seperate clock domain for components that should run at +# CPUs frequency +system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') for cpu in cpus: # create the interrupt controller cpu.createInterruptController() cpu.connectAllPorts(system.membus) - cpu.clock = '2GHz' + # All cpus are associated with cpu_clk_domain + cpu.clk_domain = system.cpu_clk_domain # connect memory to membus system.physmem.port = system.membus.master diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py index 22e1047a3..d1b471bac 100644 --- a/tests/configs/o3-timing-ruby.py +++ b/tests/configs/o3-timing-ruby.py @@ -36,13 +36,17 @@ import ruby_config ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) cpu = DerivO3CPU(cpu_id=0) -cpu.clock = '2GHz' system = System(cpu = cpu, physmem = ruby_memory, membus = CoherentBus(), - mem_mode = "timing") -system.clock = '1GHz' + mem_mode = "timing", + clk_domain = SrcClockDomain(clock = '1GHz')) + +# Create a seperate clock domain for components that should run at +# CPUs frequency +system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') + system.physmem.port = system.membus.master # create the interrupt controller cpu.createInterruptController() diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index f17083fe4..5799c0c7a 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -56,11 +56,16 @@ options.num_cpus = 2 #the system mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus, - mdesc=mdesc, Ruby=True) + mdesc=mdesc, Ruby=True, + system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)] + Ruby.create_system(options, system, system.piobus, system._dma_ports) +# Create a seperate clock domain for Ruby +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) + for (i, cpu) in enumerate(system.cpu): # create the interrupt controller cpu.createInterruptController() @@ -72,7 +77,6 @@ for (i, cpu) in enumerate(system.cpu): cpu.interrupts.pio = system.piobus.master cpu.interrupts.int_master = system.piobus.slave cpu.interrupts.int_slave = system.piobus.master - cpu.clock = '2GHz' # Set access_phys_mem to True for ruby port system.ruby._cpu_ruby_ports[i].access_phys_mem = True diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index 328337190..1553e29f4 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -77,11 +77,14 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer': tester = RubyTester(check_flush = check_flush, checks_to_complete = 100, wakeup_frequency = 10, num_cpus = options.num_cpus) -system = System(tester = tester, physmem = SimpleMemory(null = True)) -system.clock = options.sys_clock +system = System(tester = tester, physmem = SimpleMemory(null = True), + clk_domain = SrcClockDomain(clock = options.sys_clock)) Ruby.create_system(options, system) +# Create a separate clock domain for Ruby +system.ruby.clk_domain = SrcClockDomain(clock = '1GHz') + assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) # diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py index 12c26d97b..9feccb12c 100644 --- a/tests/configs/simple-atomic-mp-ruby.py +++ b/tests/configs/simple-atomic-mp-ruby.py @@ -38,13 +38,18 @@ import ruby_config ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) # system simulated -system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus()) -system.clock = '1GHz' +system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(), + clk_domain = SrcClockDomain(clock = '1GHz')) + +# Create a seperate clock domain for components that should run at +# CPUs frequency +system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') # add L1 caches for cpu in cpus: cpu.connectAllPorts(system.membus) - cpu.clock = '2GHz' + # All cpus are associated with cpu_clk_domain + cpu.clk_domain = system.cpu_clk_domain # connect memory to membus system.physmem.port = system.membus.master diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py index 2fa314d09..835428c3b 100644 --- a/tests/configs/simple-timing-mp-ruby.py +++ b/tests/configs/simple-timing-mp-ruby.py @@ -71,11 +71,18 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] options.num_cpus = nb_cores # system simulated -system = System(cpu = cpus, physmem = SimpleMemory()) -system.clock = options.sys_clock +system = System(cpu = cpus, physmem = SimpleMemory(), + clk_domain = SrcClockDomain(clock = '1GHz')) + +# Create a seperate clock domain for components that should run at +# CPUs frequency +system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') Ruby.create_system(options, system) +# Create a separate clock domain for Ruby +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) + assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) for (i, cpu) in enumerate(system.cpu): diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index 9057475a5..27d56a31d 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -67,11 +67,18 @@ options.l3_assoc=2 options.num_cpus = 1 cpu = TimingSimpleCPU(cpu_id=0) -system = System(cpu = cpu, physmem = SimpleMemory(null = True)) -system.clock = options.sys_clock +system = System(cpu = cpu, physmem = SimpleMemory(null = True), + clk_domain = SrcClockDomain(clock = '1GHz')) + +# Create a seperate clock domain for components that should run at +# CPUs frequency +system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') Ruby.create_system(options, system) +# Create a separate clock for Ruby +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) + assert(len(system.ruby._cpu_ruby_ports) == 1) # create the interrupt controller diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py index a79b65d43..394aac4cb 100644 --- a/tests/configs/tgen-simple-dram.py +++ b/tests/configs/tgen-simple-dram.py @@ -49,8 +49,8 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg") # system simulated system = System(cpu = cpu, physmem = DDR3_1600_x64(), - membus = NoncoherentBus(width = 16)) -system.clock = '1GHz' + membus = NoncoherentBus(width = 16), + clk_domain = SrcClockDomain(clock = '1GHz')) # add a communication monitor system.monitor = CommMonitor() diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py index b93165f50..2d39a2ab0 100644 --- a/tests/configs/tgen-simple-mem.py +++ b/tests/configs/tgen-simple-mem.py @@ -49,8 +49,8 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") # system simulated system = System(cpu = cpu, physmem = SimpleMemory(), - membus = NoncoherentBus(width = 16)) -system.clock = '1GHz' + membus = NoncoherentBus(width = 16), + clk_domain = SrcClockDomain(clock = '1GHz')) # add a communication monitor, and also trace all the packets system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz") diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py index 8025b4e7b..22c6686ae 100644 --- a/tests/configs/twosys-tsunami-simple-atomic.py +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -34,12 +34,22 @@ from Benchmarks import * test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory, SysConfig('netperf-stream-client.rcS')) -test_sys.clock = '1GHz' + +# Create the system clock domain +test_sys.clk_domain = SrcClockDomain(clock = '1GHz') + test_sys.cpu = AtomicSimpleCPU(cpu_id=0) # create the interrupt controller test_sys.cpu.createInterruptController() test_sys.cpu.connectAllPorts(test_sys.membus) -test_sys.cpu.clock = '2GHz' + +# Create a seperate clock domain for components that should run at +# CPUs frequency +test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz') + +# Create a separate clock domain for Ethernet +test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz') + # In contrast to the other (one-system) Tsunami configurations we do # not have an IO cache but instead rely on an IO bridge for accesses # from masters on the IO bus to the memory bus @@ -49,12 +59,20 @@ test_sys.iobridge.master = test_sys.membus.slave drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory, SysConfig('netperf-server.rcS')) -drive_sys.clock = '1GHz' +# Create the system clock domain +drive_sys.clk_domain = SrcClockDomain(clock = '1GHz') drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) # create the interrupt controller drive_sys.cpu.createInterruptController() drive_sys.cpu.connectAllPorts(drive_sys.membus) -drive_sys.cpu.clock = '4GHz' + +# Create a seperate clock domain for components that should run at +# CPUs frequency +drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz') + +# Create a separate clock domain for Ethernet +drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz') + drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges) drive_sys.iobridge.slave = drive_sys.iobus.master drive_sys.iobridge.master = drive_sys.membus.slave |