diff options
Diffstat (limited to 'tests/configs')
-rw-r--r-- | tests/configs/memtest-ruby.py | 4 | ||||
-rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 16 | ||||
-rw-r--r-- | tests/configs/rubytest-ruby.py | 4 | ||||
-rw-r--r-- | tests/configs/simple-timing-mp-ruby.py | 4 | ||||
-rw-r--r-- | tests/configs/simple-timing-ruby.py | 4 |
5 files changed, 16 insertions, 16 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index 8535a19a4..071f3a7b5 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -104,9 +104,9 @@ Ruby.create_system(options, system) system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = system.voltage_domain) -assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) +assert(len(cpus) == len(system.ruby._cpu_ports)) -for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): +for (i, ruby_port) in enumerate(system.ruby._cpu_ports): # # Tie the cpu test and functional ports to the ruby cpu ports and # physmem, respectively diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 3d1b78324..2ac571c83 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -78,16 +78,16 @@ for (i, cpu) in enumerate(system.cpu): # create the interrupt controller cpu.createInterruptController() # Tie the cpu ports to the correct ruby system ports - cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave - cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave - cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave - cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave - cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master - cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave - cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master + cpu.icache_port = system.ruby._cpu_ports[i].slave + cpu.dcache_port = system.ruby._cpu_ports[i].slave + cpu.itb.walker.port = system.ruby._cpu_ports[i].slave + cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave + cpu.interrupts.pio = system.ruby._cpu_ports[i].master + cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave + cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master # Set access_phys_mem to True for ruby port - system.ruby._cpu_ruby_ports[i].access_phys_mem = True + system.ruby._cpu_ports[i].access_phys_mem = True system.physmem = [DDR3_1600_x64(range = r) for r in system.mem_ranges] diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index 9fe85d14f..f2c88c92b 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -92,7 +92,7 @@ Ruby.create_system(options, system) system.ruby.clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = system.voltage_domain) -assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) +assert(options.num_cpus == len(system.ruby._cpu_ports)) # # The tester is most effective when randomization is turned on and @@ -100,7 +100,7 @@ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) # system.ruby.randomization = True -for ruby_port in system.ruby._cpu_ruby_ports: +for ruby_port in system.ruby._cpu_ports: # # Tie the ruby tester ports to the ruby cpu read and write ports # diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py index 835428c3b..f7dfb5c5c 100644 --- a/tests/configs/simple-timing-mp-ruby.py +++ b/tests/configs/simple-timing-mp-ruby.py @@ -83,7 +83,7 @@ Ruby.create_system(options, system) # Create a separate clock domain for Ruby system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) -assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) +assert(options.num_cpus == len(system.ruby._cpu_ports)) for (i, cpu) in enumerate(system.cpu): # create the interrupt controller @@ -92,7 +92,7 @@ for (i, cpu) in enumerate(system.cpu): # # Tie the cpu ports to the ruby cpu ports # - cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i]) + cpu.connectAllPorts(system.ruby._cpu_ports[i]) # ----------------------- # run simulation diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index 94cb15ed4..90af9c920 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -85,7 +85,7 @@ Ruby.create_system(options, system) system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = system.voltage_domain) -assert(len(system.ruby._cpu_ruby_ports) == 1) +assert(len(system.ruby._cpu_ports) == 1) # create the interrupt controller cpu.createInterruptController() @@ -94,7 +94,7 @@ cpu.createInterruptController() # Tie the cpu cache ports to the ruby cpu ports and # physmem, respectively # -cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0]) +cpu.connectAllPorts(system.ruby._cpu_ports[0]) # ----------------------- # run simulation |