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-rw-r--r--tests/configs/inorder-timing.py2
-rw-r--r--tests/configs/o3-timing-mp-ruby.py2
-rw-r--r--tests/configs/o3-timing-mp.py2
-rw-r--r--tests/configs/o3-timing-ruby.py2
-rw-r--r--tests/configs/o3-timing.py2
-rw-r--r--tests/configs/realview-simple-atomic.py2
-rw-r--r--tests/configs/realview-simple-timing.py2
-rw-r--r--tests/configs/simple-atomic-mp-ruby.py2
-rw-r--r--tests/configs/simple-atomic-mp.py2
-rw-r--r--tests/configs/simple-atomic.py2
-rw-r--r--tests/configs/simple-timing-mp.py2
-rw-r--r--tests/configs/simple-timing.py2
-rw-r--r--tests/configs/t1000-simple-atomic.py2
-rw-r--r--tests/configs/tsunami-o3-dual.py2
-rw-r--r--tests/configs/tsunami-o3.py2
-rw-r--r--tests/configs/tsunami-simple-atomic-dual.py2
-rw-r--r--tests/configs/tsunami-simple-atomic.py2
-rw-r--r--tests/configs/tsunami-simple-timing-dual.py2
-rw-r--r--tests/configs/tsunami-simple-timing.py2
-rw-r--r--tests/configs/twosys-tsunami-simple-atomic.py4
20 files changed, 21 insertions, 21 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 10f9e4232..af58cafa5 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -47,6 +47,6 @@ system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
root = Root(system = system)
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index afa46faa5..b14f0e5b1 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -40,7 +40,7 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
for cpu in cpus:
- cpu.connectMemPorts(system.membus)
+ cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index b5c720dda..5c770cdbc 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -72,7 +72,7 @@ for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- cpu.connectMemPorts(system.toL2Bus)
+ cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 40d90623a..07851ae9f 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -41,6 +41,6 @@ system = System(cpu = cpu,
physmem = ruby_memory,
membus = Bus())
system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
root = Root(system = system)
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 563772213..a4c054122 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -46,6 +46,6 @@ system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
root = Root(system = system)
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 543cb2419..c20a67df7 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -88,7 +88,7 @@ system.l2c.mem_side = system.membus.port
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
root = Root(system=system)
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index b9d00c1ee..a1e363447 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -90,7 +90,7 @@ system.l2c.mem_side = system.membus.port
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
root = Root(system=system)
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 570a1766a..705f13ef3 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -41,7 +41,7 @@ system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
# add L1 caches
for cpu in cpus:
- cpu.connectMemPorts(system.membus)
+ cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index 75ffefd08..d88a9b395 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -71,7 +71,7 @@ for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- cpu.connectMemPorts(system.toL2Bus)
+ cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index cc303886b..4a2efcc57 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -33,7 +33,7 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-system.cpu.connectMemPorts(system.membus)
+system.cpu.connectAllPorts(system.membus)
system.cpu.clock = '2GHz'
root = Root(system = system)
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 7a8da70bb..f5793b282 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -71,7 +71,7 @@ for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- cpu.connectMemPorts(system.toL2Bus)
+ cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 0ed985a17..739e11e55 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -43,7 +43,7 @@ system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
root = Root(system = system)
diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index 35b329f57..ae2c59110 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -34,7 +34,7 @@ import FSConfig
cpu = AtomicSimpleCPU(cpu_id=0)
system = FSConfig.makeSparcSystem('atomic')
system.cpu = cpu
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
root = Root(system=system)
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index d19dc9c26..7744560f9 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -92,7 +92,7 @@ for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- c.connectMemPorts(system.toL2Bus)
+ c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz'
root = Root(system=system)
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index 9b52cd92b..fd2d66431 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -90,7 +90,7 @@ system.l2c.mem_side = system.membus.port
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
root = Root(system=system)
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index d78a09db4..9d3dbaa91 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -90,7 +90,7 @@ for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- c.connectMemPorts(system.toL2Bus)
+ c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz'
root = Root(system=system)
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index cfc619b06..cbacf1995 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -88,7 +88,7 @@ system.l2c.mem_side = system.membus.port
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
root = Root(system=system)
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 13b7bf32e..f0105461d 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -90,7 +90,7 @@ for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- c.connectMemPorts(system.toL2Bus)
+ c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz'
root = Root(system=system)
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 0c3984628..9a262b3b2 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -90,7 +90,7 @@ system.l2c.mem_side = system.membus.port
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
root = Root(system=system)
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index ce191930e..7c6fde7c3 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -35,12 +35,12 @@ from Benchmarks import *
test_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-stream-client.rcS'))
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
-test_sys.cpu.connectMemPorts(test_sys.membus)
+test_sys.cpu.connectAllPorts(test_sys.membus)
drive_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-server.rcS'))
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
-drive_sys.cpu.connectMemPorts(drive_sys.membus)
+drive_sys.cpu.connectAllPorts(drive_sys.membus)
root = makeDualRoot(test_sys, drive_sys, "ethertrace")
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 15:59:29 +0000