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-rw-r--r--tests/configs/inorder-timing.py6
-rw-r--r--tests/configs/memtest.py1
-rw-r--r--tests/configs/o3-timing-mp.py1
-rw-r--r--tests/configs/o3-timing.py6
-rw-r--r--tests/configs/pc-simple-atomic.py3
-rw-r--r--tests/configs/pc-simple-timing.py1
-rw-r--r--tests/configs/realview-o3.py99
-rw-r--r--tests/configs/realview-simple-atomic.py1
-rw-r--r--tests/configs/realview-simple-timing.py1
-rw-r--r--tests/configs/simple-atomic-mp.py1
-rw-r--r--tests/configs/simple-timing-mp.py1
-rw-r--r--tests/configs/simple-timing.py6
-rw-r--r--tests/configs/tsunami-o3-dual.py2
-rw-r--r--tests/configs/tsunami-o3.py2
-rw-r--r--tests/configs/tsunami-simple-atomic-dual.py2
-rw-r--r--tests/configs/tsunami-simple-atomic.py2
-rw-r--r--tests/configs/tsunami-simple-timing-dual.py2
-rw-r--r--tests/configs/tsunami-simple-timing.py2
18 files changed, 136 insertions, 3 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index af58cafa5..ddf37b5ec 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -37,8 +37,12 @@ class MyCache(BaseCache):
mshrs = 10
tgts_per_mshr = 5
+class MyL1Cache(MyCache):
+ is_top_level = True
+
cpu = InOrderCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+ MyL1Cache(size = '256kB'),
MyCache(size = '2MB', latency='10ns'))
cpu.clock = '2GHz'
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index d75bd3d8c..f62381473 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -38,6 +38,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 12
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 5c770cdbc..35811282c 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -39,6 +39,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index a4c054122..d4a69d94a 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -37,8 +37,12 @@ class MyCache(BaseCache):
mshrs = 10
tgts_per_mshr = 5
+class MyL1Cache(MyCache):
+ is_top_level = True
+
cpu = DerivO3CPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+ MyL1Cache(size = '256kB'),
MyCache(size = '2MB'))
cpu.clock = '2GHz'
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index 382899eb5..1c35ff2d9 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -43,6 +43,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
@@ -65,6 +66,7 @@ class PageTableWalkerCache(BaseCache):
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
+ is_top_level = True
# ---------------------
# I/O Cache
@@ -78,6 +80,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range = AddrRange(0, size=mem_size)
forward_snoops = False
+ is_top_level = True
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index 7452e2542..9c9f4aeca 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -44,6 +44,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
new file mode 100644
index 000000000..2d805fe0a
--- /dev/null
+++ b/tests/configs/realview-o3.py
@@ -0,0 +1,99 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+import FSConfig
+
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = '1ns'
+ block_size = 64
+ mshrs = 4
+ tgts_per_mshr = 8
+ is_top_level = True
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = '10ns'
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ latency = '50ns'
+ mshrs = 20
+ size = '1kB'
+ tgts_per_mshr = 12
+ addr_range=AddrRange(0, size='128MB')
+ forward_snoops = False
+
+#cpu
+cpu = DerivO3CPU(cpu_id=0)
+#the system
+system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
+
+system.cpu = cpu
+#create the l1/l2 bus
+system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
+
+#connect up the l2 cache
+system.l2c = L2(size='4MB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.mem_side = system.membus.port
+
+#connect up the cpu and l1s
+cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4))
+# connect cpu level-1 caches to shared level-2 cache
+cpu.connectAllPorts(system.toL2Bus, system.membus)
+cpu.clock = '2GHz'
+
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('1THz')
+
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index ab6d612d4..7340be7a4 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -40,6 +40,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 53b6ab2b2..83b643c52 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -41,6 +41,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index d88a9b395..4db741b8a 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -38,6 +38,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index f5793b282..6f4090ec2 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -38,6 +38,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 739e11e55..bc9d016c5 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -36,8 +36,12 @@ class MyCache(BaseCache):
mshrs = 10
tgts_per_mshr = 5
+class MyL1Cache(MyCache):
+ is_top_level = True
+
cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+ MyL1Cache(size = '256kB'),
MyCache(size = '2MB', latency='10ns'))
system = System(cpu = cpu,
physmem = PhysicalMemory(),
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index 7744560f9..125e228a7 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -41,6 +41,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
@@ -65,6 +66,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
+ is_top_level = True
#cpu
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index fd2d66431..13212d5d9 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -41,6 +41,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
@@ -65,6 +66,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
+ is_top_level = True
#cpu
cpu = DerivO3CPU(cpu_id=0)
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 9d3dbaa91..2e56ce851 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -40,6 +40,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
@@ -64,6 +65,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
+ is_top_level = True
#cpu
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index cbacf1995..3c1981464 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -40,6 +40,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
@@ -64,6 +65,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
+ is_top_level = True
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index f0105461d..747cdac18 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -40,6 +40,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
@@ -64,6 +65,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
+ is_top_level = True
#cpu
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 9a262b3b2..110e6ee74 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -41,6 +41,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
@@ -65,6 +66,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range=AddrRange(0, size='8GB')
forward_snoops = False
+ is_top_level = True
#cpu
cpu = TimingSimpleCPU(cpu_id=0)
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-17 12:48:08 +0000