5 files changed, 5 insertions, 5 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index a92c61ba1..77c4f3d18 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -39,7 +39,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
-                physmem = SimpleDRAM(),
+                physmem = SimpleDDR3(),
                 membus = CoherentBus(),
                 mem_mode = "timing")
 system.system_port = system.membus.slave
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index a33a2ac06..cd15cf66b 100644
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -52,7 +52,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
-                physmem = SimpleDRAM(),
+                physmem = SimpleDDR3(),
                 membus = CoherentBus(),
                 mem_mode = "timing")
 system.system_port = system.membus.slave
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index c3a4929bb..59f91a392 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -36,7 +36,7 @@ cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus,
-                physmem = SimpleDRAM(),
+                physmem = SimpleDDR3(),
                 membus = CoherentBus(),
                 mem_mode = "timing")
 
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 474d13902..8c3c9abe7 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -41,7 +41,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
-                physmem = SimpleDRAM(),
+                physmem = SimpleDDR3(),
                 membus = CoherentBus(),
                 mem_mode = "timing")
 system.system_port = system.membus.slave
diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py
index 0e9edc171..19eb15933 100644
--- a/tests/configs/tgen-simple-dram.py
+++ b/tests/configs/tgen-simple-dram.py
@@ -48,7 +48,7 @@ require_sim_object("CommMonitor")
 cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
 
 # system simulated
-system = System(cpu = cpu, physmem = SimpleDRAM(),
+system = System(cpu = cpu, physmem = SimpleDDR3(),
                 membus = NoncoherentBus(clock="1GHz", width = 16))
 
 # add a communication monitor