diff options
Diffstat (limited to 'tests/configs')
25 files changed, 178 insertions, 171 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py index af7609e9f..5f2156ff9 100644 --- a/tests/configs/inorder-timing.py +++ b/tests/configs/inorder-timing.py @@ -33,8 +33,8 @@ m5.util.addToPath('../configs/common') class MyCache(BaseCache): assoc = 2 block_size = 64 - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 mshrs = 10 tgts_per_mshr = 5 @@ -44,8 +44,8 @@ class MyL1Cache(MyCache): cpu = InOrderCPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), MyL1Cache(size = '256kB'), - MyCache(size = '2MB', hit_latency='10ns', - response_latency='10ns')) + MyCache(size = '2MB', hit_latency = 20, + response_latency = 20)) cpu.clock = '2GHz' diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index 5d60ee0ea..4db2d4f2a 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -34,8 +34,8 @@ from m5.objects import * # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -47,8 +47,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -65,7 +65,7 @@ system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), # l2cache & bus system.toL2Bus = CoherentBus(clock="2GHz", width=16) -system.l2c = L2(size='64kB', assoc=8) +system.l2c = L2(clock = '2GHz', size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py index 866d57851..a54c9b7ca 100644 --- a/tests/configs/o3-timing-checker.py +++ b/tests/configs/o3-timing-checker.py @@ -42,8 +42,8 @@ m5.util.addToPath('../configs/common') class MyCache(BaseCache): assoc = 2 block_size = 64 - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 mshrs = 10 tgts_per_mshr = 5 @@ -57,6 +57,9 @@ cpu.addCheckerCpu() cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), MyL1Cache(size = '256kB'), MyCache(size = '2MB')) +# @todo Note that the L2 latency here is unmodified and 2 cycles, +# should set hit latency and response latency to 20 cycles as for +# other scripts cpu.clock = '2GHz' system = System(cpu = cpu, diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 1b3207311..0b10f5766 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -35,8 +35,8 @@ m5.util.addToPath('../configs/common') # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 20 @@ -48,8 +48,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -61,8 +61,8 @@ cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) # l2cache & bus -system.toL2Bus = CoherentBus() -system.l2c = L2(size='4MB', assoc=8) +system.toL2Bus = CoherentBus(clock = '2GHz') +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index 0646f1c26..f87e0e355 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -33,8 +33,8 @@ m5.util.addToPath('../configs/common') class MyCache(BaseCache): assoc = 2 block_size = 64 - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 mshrs = 10 tgts_per_mshr = 5 @@ -46,6 +46,9 @@ cpu = DerivO3CPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), MyL1Cache(size = '256kB'), MyCache(size = '2MB')) +# @todo Note that the L2 latency here is unmodified and 2 cycles, +# should set hit latency and response latency to 20 cycles as for +# other scripts cpu.clock = '2GHz' system = System(cpu = cpu, diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py index f75c5776d..729f3bd8f 100644 --- a/tests/configs/pc-o3-timing.py +++ b/tests/configs/pc-o3-timing.py @@ -39,8 +39,8 @@ mem_size = '128MB' # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 20 @@ -52,8 +52,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -64,8 +64,8 @@ class L2(BaseCache): class PageTableWalkerCache(BaseCache): assoc = 2 block_size = 64 - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 mshrs = 10 size = '1kB' tgts_per_mshr = 12 @@ -76,8 +76,8 @@ class PageTableWalkerCache(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -94,7 +94,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py index b628992ec..7dfec362e 100644 --- a/tests/configs/pc-simple-atomic.py +++ b/tests/configs/pc-simple-atomic.py @@ -39,8 +39,8 @@ mem_size = '128MB' # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -52,8 +52,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -64,8 +64,8 @@ class L2(BaseCache): class PageTableWalkerCache(BaseCache): assoc = 2 block_size = 64 - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 mshrs = 10 size = '1kB' tgts_per_mshr = 12 @@ -77,8 +77,8 @@ class PageTableWalkerCache(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -96,7 +96,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index 8a44300e5..bfbf926dc 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -40,8 +40,8 @@ mem_size = '128MB' # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -53,8 +53,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -65,8 +65,8 @@ class L2(BaseCache): class PageTableWalkerCache(BaseCache): assoc = 2 block_size = 64 - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 mshrs = 10 size = '1kB' tgts_per_mshr = 12 @@ -77,8 +77,8 @@ class PageTableWalkerCache(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -95,7 +95,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py index 961a4a698..a791b3983 100644 --- a/tests/configs/realview-o3-checker.py +++ b/tests/configs/realview-o3-checker.py @@ -46,8 +46,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 20 @@ -59,8 +59,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -71,8 +71,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -89,7 +89,7 @@ system.cpu = cpu cpu.addCheckerCpu() #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py index aa756c07f..599ef6f8c 100644 --- a/tests/configs/realview-o3-dual.py +++ b/tests/configs/realview-o3-dual.py @@ -37,8 +37,8 @@ from Benchmarks import * # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 20 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -74,16 +74,16 @@ class IOCache(BaseCache): cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus -system.toL2Bus = CoherentBus() +system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(size='4MB', assoc=8) +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index 24e5ca82b..698c6dd14 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -37,8 +37,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 20 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -78,7 +78,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py index 67d0c2f32..9bf2fd70d 100644 --- a/tests/configs/realview-simple-atomic-dual.py +++ b/tests/configs/realview-simple-atomic-dual.py @@ -37,8 +37,8 @@ from Benchmarks import * # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -74,16 +74,16 @@ class IOCache(BaseCache): cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus -system.toL2Bus = CoherentBus() +system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(size='4MB', assoc=8) +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py index 55c5d2409..05ef0dd63 100644 --- a/tests/configs/realview-simple-atomic.py +++ b/tests/configs/realview-simple-atomic.py @@ -36,8 +36,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -49,8 +49,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -61,8 +61,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -77,7 +77,7 @@ system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py index 939602fb5..ee5ffaf06 100644 --- a/tests/configs/realview-simple-timing-dual.py +++ b/tests/configs/realview-simple-timing-dual.py @@ -37,8 +37,8 @@ from Benchmarks import * # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -74,16 +74,16 @@ class IOCache(BaseCache): cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus -system.toL2Bus = CoherentBus() +system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(size='4MB', assoc=8) +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py index b5db3e10b..28cd3163f 100644 --- a/tests/configs/realview-simple-timing.py +++ b/tests/configs/realview-simple-timing.py @@ -37,8 +37,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -78,7 +78,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index 6c86eff2d..6dde4ed68 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -34,8 +34,8 @@ from m5.objects import * # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -47,8 +47,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ system = System(cpu = cpus, membus = CoherentBus()) # l2cache & bus -system.toL2Bus = CoherentBus() -system.l2c = L2(size='4MB', assoc=8) +system.toL2Bus = CoherentBus(clock = '2GHz') +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 559cf807a..3e5e92d8c 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -34,8 +34,8 @@ from m5.objects import * # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -47,8 +47,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -60,8 +60,8 @@ cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) # l2cache & bus -system.toL2Bus = CoherentBus() -system.l2c = L2(size='4MB', assoc=8) +system.toL2Bus = CoherentBus(clock = '2GHz') +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index cb40ca5c3..beeadced9 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -32,8 +32,8 @@ from m5.objects import * class MyCache(BaseCache): assoc = 2 block_size = 64 - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 mshrs = 10 tgts_per_mshr = 5 @@ -43,7 +43,8 @@ class MyL1Cache(MyCache): cpu = TimingSimpleCPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), MyL1Cache(size = '256kB'), - MyCache(size = '2MB', hit_latency='10ns', response_latency ='10ns')) + MyCache(size = '2MB', hit_latency= 20, + response_latency = 20)) system = System(cpu = cpu, physmem = SimpleMemory(), membus = CoherentBus()) diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py index b32a1ff17..163ac3ba6 100644 --- a/tests/configs/tsunami-inorder.py +++ b/tests/configs/tsunami-inorder.py @@ -37,8 +37,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -82,7 +82,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py index a40c44c9b..5ba14753d 100644 --- a/tests/configs/tsunami-o3-dual.py +++ b/tests/configs/tsunami-o3-dual.py @@ -37,8 +37,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 20 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -78,14 +78,14 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpus #create the l1/l2 bus -system.toL2Bus = CoherentBus() -system.iocache = IOCache() +system.toL2Bus = CoherentBus(clock = '2GHz') +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the l2 cache -system.l2c = L2(size='4MB', assoc=8) +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py index 75ff66218..2920c878a 100644 --- a/tests/configs/tsunami-o3.py +++ b/tests/configs/tsunami-o3.py @@ -37,8 +37,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 20 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -79,7 +79,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index e08a1ee0d..851ec847b 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -36,8 +36,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -49,8 +49,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -61,8 +61,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -74,16 +74,16 @@ class IOCache(BaseCache): cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeLinuxAlphaSystem('atomic') -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus -system.toL2Bus = CoherentBus() +system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(size='4MB', assoc=8) +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 7d8743493..c583f9d2b 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -36,8 +36,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -49,8 +49,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -61,8 +61,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -78,7 +78,7 @@ system = FSConfig.makeLinuxAlphaSystem('atomic') system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 71d231e58..e69db3438 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -36,8 +36,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -49,8 +49,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -61,8 +61,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -74,16 +74,16 @@ class IOCache(BaseCache): cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] #the system system = FSConfig.makeLinuxAlphaSystem('timing') -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave system.cpu = cpus #create the l1/l2 bus -system.toL2Bus = CoherentBus() +system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(size='4MB', assoc=8) +system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index b6378eb61..e71d75846 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -37,8 +37,8 @@ import FSConfig # ==================== class L1(BaseCache): - hit_latency = '1ns' - response_latency = '1ns' + hit_latency = 2 + response_latency = 2 block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -50,8 +50,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - hit_latency = '10ns' - response_latency = '10ns' + hit_latency = 20 + response_latency = 20 mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,8 +62,8 @@ class L2(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - hit_latency = '50ns' - response_latency = '50ns' + hit_latency = 50 + response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 @@ -79,7 +79,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing') system.cpu = cpu #create the iocache -system.iocache = IOCache() +system.iocache = IOCache(clock = '1GHz') system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave |