5 files changed, 11 insertions, 11 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 08b73cd2f..badd64e63 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -98,7 +98,7 @@ for cpu in cpus:
 
 system.mem_ranges = AddrRange('256MB')
 
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
 
 # Create a separate clock domain for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 2ac571c83..633a19e2f 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -68,12 +68,16 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
 system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
               for i in xrange(options.num_cpus)]
 
-Ruby.create_system(options, system, system.iobus, system._dma_ports)
+Ruby.create_system(options, True, system, system.iobus, system._dma_ports)
 
 # Create a seperate clock domain for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
                                         voltage_domain = system.voltage_domain)
 
+# Connect the ruby io port to the PIO bus,
+# assuming that there is just one such port.
+system.iobus.master = system.ruby._io_port.slave
+
 for (i, cpu) in enumerate(system.cpu):
     # create the interrupt controller
     cpu.createInterruptController()
@@ -82,17 +86,13 @@ for (i, cpu) in enumerate(system.cpu):
     cpu.dcache_port = system.ruby._cpu_ports[i].slave
     cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
     cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
+
     cpu.interrupts.pio = system.ruby._cpu_ports[i].master
     cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave
     cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master
 
-    # Set access_phys_mem to True for ruby port
-    system.ruby._cpu_ports[i].access_phys_mem = True
-
-system.physmem = [DDR3_1600_x64(range = r)
+system.physmem = [SimpleMemory(range = r, null = True)
                   for r in system.mem_ranges]
-for i in xrange(len(system.physmem)):
-    system.physmem[i].port = system.iobus.master
 
 root = Root(full_system = True, system = system)
 m5.ticks.setGlobalFrequency('1THz')
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index b3d3f0363..cbb578938 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -89,7 +89,7 @@ system.clk_domain = SrcClockDomain(clock = '1GHz',
 
 system.mem_ranges = AddrRange('256MB')
 
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
 
 # Create a separate clock domain for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index f7dfb5c5c..da7733acb 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -78,7 +78,7 @@ system = System(cpu = cpus, physmem = SimpleMemory(),
 # CPUs frequency
 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
 
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
 
 # Create a separate clock domain for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 90af9c920..3ce6266c1 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -79,7 +79,7 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
                                        voltage_domain = system.voltage_domain)
 
 system.mem_ranges = AddrRange('256MB')
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
 
 # Create a separate clock for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,