diff options
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt')
| -rw-r--r-- | tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt | 36 |
1 files changed, 26 insertions, 10 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index 5453dc099..c668a0459 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 963880 # Simulator instruction rate (inst/s) -host_mem_usage 148548 # Number of bytes of host memory used -host_seconds 624.41 # Real time elapsed on the host -host_tick_rate 481939681 # Simulator tick rate (ticks/s) +host_inst_rate 2906348 # Simulator instruction rate (inst/s) +host_mem_usage 174252 # Number of bytes of host memory used +host_seconds 207.08 # Real time elapsed on the host +host_tick_rate 1453183573 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.300928 # Number of seconds simulated -sim_ticks 300928482000 # Number of ticks simulated +sim_insts 601856964 # Number of instructions simulated +sim_seconds 0.300931 # Number of seconds simulated +sim_ticks 300930958000 # Number of ticks simulated +system.cpu.dtb.accesses 153970296 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 153965363 # DTB hits +system.cpu.dtb.misses 4933 # DTB misses +system.cpu.dtb.read_accesses 114516673 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 114514042 # DTB read hits +system.cpu.dtb.read_misses 2631 # DTB read misses +system.cpu.dtb.write_accesses 39453623 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 39451321 # DTB write hits +system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 601861917 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 601861897 # ITB hits +system.cpu.itb.misses 20 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 601856965 # number of cpu cycles simulated -system.cpu.num_insts 601856965 # Number of instructions executed -system.cpu.num_refs 154862034 # Number of memory references +system.cpu.numCycles 601861917 # number of cpu cycles simulated +system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- |