diff options
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt')
| -rw-r--r-- | tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt | 40 |
1 files changed, 28 insertions, 12 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index d5f13f08c..aa16ad6b4 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,17 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6175770 # Simulator instruction rate (inst/s) -host_mem_usage 195684 # Number of bytes of host memory used -host_seconds 97.45 # Real time elapsed on the host -host_tick_rate 3087904278 # Simulator tick rate (ticks/s) +host_inst_rate 5975527 # Simulator instruction rate (inst/s) +host_mem_usage 197448 # Number of bytes of host memory used +host_seconds 100.72 # Real time elapsed on the host +host_tick_rate 2987780856 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated sim_ticks 300930958000 # Number of ticks simulated -system.cpu.dtb.accesses 153970296 # DTB accesses -system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 153965363 # DTB hits -system.cpu.dtb.misses 4933 # DTB misses +system.cpu.dtb.data_accesses 153970296 # DTB accesses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_hits 153965363 # DTB hits +system.cpu.dtb.data_misses 4933 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 114516673 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_hits 114514042 # DTB read hits @@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 39451321 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 601861917 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 601861897 # ITB hits -system.cpu.itb.misses 20 # ITB misses +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 601861917 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 601861897 # ITB hits +system.cpu.itb.fetch_misses 20 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 601861917 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed |