diff options
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64/simple-timing')
4 files changed, 105 insertions, 98 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index fdd3515e5..850a6530b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -152,12 +152,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr index b2d79346c..67f69f09d 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index c1023446a..d9a9a6b92 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:27:06 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:59:22 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -44,3 +46,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! +Exiting @ tick 777351681000 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 53f0d7951..c92f137ce 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1555765 # Simulator instruction rate (inst/s) -host_mem_usage 191800 # Number of bytes of host memory used -host_seconds 386.86 # Real time elapsed on the host -host_tick_rate 2011092592 # Simulator tick rate (ticks/s) +host_inst_rate 1386497 # Simulator instruction rate (inst/s) +host_mem_usage 206712 # Number of bytes of host memory used +host_seconds 434.08 # Real time elapsed on the host +host_tick_rate 1790782589 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.778004 # Number of seconds simulated -sim_ticks 778003833000 # Number of ticks simulated +sim_seconds 0.777352 # Number of seconds simulated +sim_ticks 777351681000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21007.583287 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18007.583287 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4227398000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3623702000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 54405.858739 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51405.858739 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 39124493 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17781358000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.008284 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 326828 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16800874000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008284 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 326828 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses -system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 41678.513805 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153437303 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 22008756000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003430 # miss rate for demand accesses +system.cpu.dcache.demand_misses 528060 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 20424576000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003430 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 528060 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999559 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.195523 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999560 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.197079 # Average occupied blocks per context system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 41678.513805 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153435240 # number of overall hits -system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses -system.cpu.dcache.overall_misses 530123 # number of overall misses +system.cpu.dcache.overall_hits 153437303 # number of overall hits +system.cpu.dcache.overall_miss_latency 22008756000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003430 # miss rate for overall accesses +system.cpu.dcache.overall_misses 528060 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 20424576000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003430 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 528060 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.197079 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 325723 # number of writebacks +system.cpu.dcache.warmup_cycle 578599000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 325740 # number of writebacks system.cpu.dtb.data_accesses 153970296 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 153965363 # DTB hits @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 795 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.328723 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 673.225223 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.328737 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 673.252668 # Average occupied blocks per context system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.252668 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,36 +164,37 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 12405 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 12571416000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.951193 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 241758 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9670320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.951193 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 241758 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 167657 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1787240000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.170126 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34370 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1374800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170126 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34370 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 72665 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 3778580000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 72665 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2906600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 72665 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 325740 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 325740 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.553777 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -202,44 +203,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 180062 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14358656000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.605292 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 276128 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11045120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.605292 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 276128 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.050771 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.447994 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1663.663316 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14679.879055 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.052155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.448358 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1709.012624 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14691.802112 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 167236 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 288954 # number of overall misses +system.cpu.l2cache.overall_hits 180062 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14358656000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.605292 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 276128 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11045120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.605292 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 276128 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 84513 # number of replacements -system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 83906 # number of replacements +system.cpu.l2cache.sampled_refs 99616 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use -system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16400.814735 # Cycle average of tags in use +system.cpu.l2cache.total_refs 354013 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63194 # number of writebacks +system.cpu.l2cache.writebacks 62672 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1556007666 # number of cpu cycles simulated +system.cpu.numCycles 1554703362 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls |