diff options
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64/simple-timing')
| -rw-r--r-- | tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini | 12 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt | 60 |
2 files changed, 49 insertions, 23 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 16b6c6fda..21fbe2323 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index eaccc0729..b76b4e6c1 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1799420 # Simulator instruction rate (inst/s) -host_mem_usage 199568 # Number of bytes of host memory used -host_seconds 334.47 # Real time elapsed on the host -host_tick_rate 2297009943 # Simulator tick rate (ticks/s) +host_inst_rate 1730291 # Simulator instruction rate (inst/s) +host_mem_usage 181616 # Number of bytes of host memory used +host_seconds 347.84 # Real time elapsed on the host +host_tick_rate 2208778962 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.768288 # Number of seconds simulated -sim_ticks 768287940000 # Number of ticks simulated +sim_insts 601856964 # Number of instructions simulated +sim_seconds 0.768293 # Number of seconds simulated +sim_ticks 768292872000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 23626.361612 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21626.361612 # average ReadReq mshr miss latency @@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.970134 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.968001 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 342925000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 343385000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks -system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 153970296 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 153965363 # DTB hits +system.cpu.dtb.misses 4933 # DTB misses +system.cpu.dtb.read_accesses 114516673 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 114514042 # DTB read hits +system.cpu.dtb.read_misses 2631 # DTB read misses +system.cpu.dtb.write_accesses 39453623 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 39451321 # DTB write hits +system.cpu.dtb.write_misses 2302 # DTB write misses +system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 19875000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses @@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 757051.787421 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency -system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits +system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 19875000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses @@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 795 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 601856171 # number of overall hits +system.cpu.icache.overall_hits 601861103 # number of overall hits system.cpu.icache.overall_miss_latency 19875000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.685789 # Cycle average of tags in use -system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 673.685273 # Cycle average of tags in use +system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 601861918 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 601861898 # ITB hits +system.cpu.itb.misses 20 # ITB misses system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 13394 # number of replacements system.cpu.l2cache.sampled_refs 14881 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8423.446687 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 8423.428104 # Cycle average of tags in use system.cpu.l2cache.total_refs 52084 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 768287940000 # number of cpu cycles simulated -system.cpu.num_insts 601856965 # Number of instructions executed -system.cpu.num_refs 154862034 # Number of memory references +system.cpu.numCycles 768292872000 # number of cpu cycles simulated +system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- |