diff options
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64')
11 files changed, 125 insertions, 35 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index ed1344dd3..41c6a83e0 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index a359bdb55..5ab603e64 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:40:29 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:50 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 240486239..9ddf470e4 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 207877 # Simulator instruction rate (inst/s) -host_mem_usage 206352 # Number of bytes of host memory used -host_seconds 2720.61 # Real time elapsed on the host -host_tick_rate 59832123 # Simulator tick rate (ticks/s) +host_inst_rate 121046 # Simulator instruction rate (inst/s) +host_mem_usage 226784 # Number of bytes of host memory used +host_seconds 4672.20 # Real time elapsed on the host +host_tick_rate 34840083 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162780 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed +system.cpu.commit.COM:fp_insts 1520 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 1197610 # Number of function calls committed. +system.cpu.commit.COM:int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.COM:loads 114514042 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 153965363 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 325492829 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 265 # number of floating regfile reads +system.cpu.fp_regfile_writes 58 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 65560315 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36252.118644 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 3177577 # system.cpu.iew.memOrderViolationEvents 70243 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 943658 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3659139 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 844691087 # number of integer regfile reads +system.cpu.int_regfile_writes 489153092 # number of integer regfile writes system.cpu.ipc 1.737170 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.737170 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 325492829 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.859166 # Inst issue rate +system.cpu.iq.fp_alu_accesses 1679 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 3330 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 1605 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 1800 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 612363224 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1543136462 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 595804344 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 671661588 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 619293624 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 605269413 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ @@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 17165638 # Nu system.cpu.memDep0.conflictingStores 12779208 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 126095826 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 42628898 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 325559560 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 12578826 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 31670463 # Number of times rename has blocked due to IQ full @@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 115552585 # Nu system.cpu.rename.RENAME:SquashCycles 9698747 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 37704265 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 54254608 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 1958 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 894826947 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 531 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 73685603 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 29 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 958179178 # The number of ROB reads +system.cpu.rob.rob_writes 1334457472 # The number of ROB writes system.cpu.timesIdled 2072 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index d0f6032a2..355960d42 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout index 635701ab6..b96d561c3 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:31:02 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 739ca9c21..4dfa82a45 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6224890 # Simulator instruction rate (inst/s) -host_mem_usage 232016 # Number of bytes of host memory used -host_seconds 96.69 # Real time elapsed on the host -host_tick_rate 3112463113 # Simulator tick rate (ticks/s) +host_inst_rate 1697811 # Simulator instruction rate (inst/s) +host_mem_usage 218112 # Number of bytes of host memory used +host_seconds 354.49 # Real time elapsed on the host +host_tick_rate 848911876 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 601861917 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 601861917 # Number of busy cycles +system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses +system.cpu.num_fp_insts 1520 # number of float instructions +system.cpu.num_fp_register_reads 169 # number of times the floating registers were read +system.cpu.num_fp_register_writes 42 # number of times the floating registers were written +system.cpu.num_func_calls 2395217 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 153970296 # Number of memory references +system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses +system.cpu.num_int_insts 563959696 # number of integer instructions +system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read +system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written +system.cpu.num_load_insts 114516673 # Number of load instructions +system.cpu.num_mem_refs 153970296 # number of memory refs +system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 6ed9b214f..5dbdc6426 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 15443bcd3..5133de4f2 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:44:32 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:36 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index d095a4f5f..0f44a109b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2723974 # Simulator instruction rate (inst/s) -host_mem_usage 239668 # Number of bytes of host memory used -host_seconds 220.95 # Real time elapsed on the host -host_tick_rate 3465167347 # Simulator tick rate (ticks/s) +host_inst_rate 591495 # Simulator instruction rate (inst/s) +host_mem_usage 225828 # Number of bytes of host memory used +host_seconds 1017.52 # Real time elapsed on the host +host_tick_rate 752441266 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.765623 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 59341 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1531246064 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1531246064 # Number of busy cycles +system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses +system.cpu.num_fp_insts 1520 # number of float instructions +system.cpu.num_fp_register_reads 169 # number of times the floating registers were read +system.cpu.num_fp_register_writes 42 # number of times the floating registers were written +system.cpu.num_func_calls 2395217 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 153970296 # Number of memory references +system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses +system.cpu.num_int_insts 563959696 # number of integer instructions +system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read +system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written +system.cpu.num_load_insts 114516673 # Number of load instructions +system.cpu.num_mem_refs 153970296 # number of memory refs +system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- |