diff options
Diffstat (limited to 'tests/long/00.gzip/ref/alpha/tru64')
6 files changed, 593 insertions, 589 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 23a53cd4f..b6c1d1a1d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout index 52e5d9fa3..9da502021 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:12:22 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:24 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 279017416500 because target called exit() +Exiting @ tick 274500333500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index a0423dfde..ec1428295 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279017 # Number of seconds simulated -sim_ticks 279017416500 # Number of ticks simulated +sim_seconds 0.274500 # Number of seconds simulated +sim_ticks 274500333500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128000 # Simulator instruction rate (inst/s) -host_tick_rate 59339940 # Simulator tick rate (ticks/s) -host_mem_usage 192984 # Number of bytes of host memory used -host_seconds 4702.02 # Real time elapsed on the host +host_inst_rate 56944 # Simulator instruction rate (inst/s) +host_tick_rate 25971361 # Simulator tick rate (ticks/s) +host_mem_usage 245756 # Number of bytes of host memory used +host_seconds 10569.35 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517555 # DTB read hits +system.cpu.dtb.read_hits 114517568 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520186 # DTB read accesses -system.cpu.dtb.write_hits 39666604 # DTB write hits +system.cpu.dtb.read_accesses 114520199 # DTB read accesses +system.cpu.dtb.write_hits 39666597 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668906 # DTB write accesses -system.cpu.dtb.data_hits 154184159 # DTB hits +system.cpu.dtb.write_accesses 39668899 # DTB write accesses +system.cpu.dtb.data_hits 154184165 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189092 # DTB accesses -system.cpu.itb.fetch_hits 29078095 # ITB hits +system.cpu.dtb.data_accesses 154189098 # DTB accesses +system.cpu.itb.fetch_hits 27986226 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 29078117 # ITB accesses +system.cpu.itb.fetch_accesses 27986248 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 558034834 # number of cpu cycles simulated +system.cpu.numCycles 549000668 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 547808694 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412073 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61249901 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 496784933 # Number of cycles cpu stages are processed. -system.cpu.activity 89.024000 # Percentage of cycles cpu is active +system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed. +system.cpu.activity 89.164571 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -61,79 +61,79 @@ system.cpu.comFloats 24 # Nu system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total) -system.cpu.cpi 0.927188 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.927188 # CPI: Total CPI of All Threads -system.cpu.ipc 1.078529 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads +system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.078529 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 90037625 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 84897563 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 39773148 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 49497029 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 39091844 # Number of BTB hits +system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 78.978163 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 41686827 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 48350798 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541420411 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005275257 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 257533113 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 154627572 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 38276366 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1491795 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 39768161 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 22779717 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 63.580352 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 411890550 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 154582342 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 210144173 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 347890661 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.342105 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 246346046 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 311688788 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 55.854719 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 214904658 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 343130176 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 61.489025 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 446207500 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111827334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.039490 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 210384695 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347650139 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 62.299003 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 726.393228 # Cycle average of tags in use -system.cpu.icache.total_refs 29077078 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 852 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 34128.025822 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use +system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 726.393228 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.354684 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 29077078 # number of ReadReq hits -system.cpu.icache.demand_hits 29077078 # number of demand (read+write) hits -system.cpu.icache.overall_hits 29077078 # number of overall hits -system.cpu.icache.ReadReq_misses 1015 # number of ReadReq misses -system.cpu.icache.demand_misses 1015 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1015 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 56421500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 56421500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 56421500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 29078093 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 29078093 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 29078093 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55587.684729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55587.684729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55587.684729 # average overall miss latency +system.cpu.icache.occ_blocks::0 728.259897 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.355596 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 27985205 # number of ReadReq hits +system.cpu.icache.demand_hits 27985205 # number of demand (read+write) hits +system.cpu.icache.overall_hits 27985205 # number of overall hits +system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses +system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 56646500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 56646500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 56646500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 27986224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 27986224 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 27986224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000036 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000036 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55590.284593 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55590.284593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55590.284593 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -143,159 +143,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets 21750 system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 163 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 163 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 163 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 852 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 852 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 852 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 855 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 855 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45615500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45615500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45615500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45774000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45774000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45774000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53539.319249 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.156589 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394384 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use +system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.642199 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267634000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.156589 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999550 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114120508 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38273876 # number of WriteReq hits -system.cpu.dcache.demand_hits 152394384 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 152394384 # number of overall hits -system.cpu.dcache.ReadReq_misses 393534 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1177445 # number of WriteReq misses -system.cpu.dcache.demand_misses 1570979 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1570979 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 8150455500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25241828500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 33392284000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 33392284000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.126386 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 114120509 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38273735 # number of WriteReq hits +system.cpu.dcache.demand_hits 152394244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 152394244 # number of overall hits +system.cpu.dcache.ReadReq_misses 393533 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1177586 # number of WriteReq misses +system.cpu.dcache.demand_misses 1571119 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1571119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 8150453500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25245531000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 33395984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 33395984500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.029846 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010203 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20710.930949 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 21437.798369 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 21255.716340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 21255.716340 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12054000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3423892000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2783 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216217 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4331.297161 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15835.443097 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate 0.029849 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 21256.177603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 21256.177603 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 216245 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408187 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 192302 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 923282 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1115584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1115584 # number of overall MSHR hits +system.cpu.dcache.writebacks 408188 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 192301 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 923423 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1115724 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1115724 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3562178000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5466807000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9028985000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9028985000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3562138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5466740000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9028878000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9028878000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.846625 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21509.059147 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73794 # number of replacements -system.cpu.l2cache.tagsinuse 17696.077368 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445682 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89681 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.969637 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73797 # number of replacements +system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use +system.cpu.l2cache.total_refs 445688 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1642.043968 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16054.033399 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.050111 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.489930 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170050 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408187 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364155 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364155 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32017 # number of ReadReq misses +system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 364156 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92092 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92092 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1674832000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3134450000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4809282000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4809282000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202067 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408187 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92094 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456247 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456247 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158447 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201847 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201847 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52310.709935 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.613816 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52222.581766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52222.581766 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1314000 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10346.456693 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59344 # number of writebacks +system.cpu.l2cache.writebacks 59345 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32017 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92092 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92092 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1280946000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406895000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3687841000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3687841000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201847 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201847 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.308086 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.835622 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 2c97093b4..55c96d241 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 8c9b1bbab..ac32dbe3f 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:20:02 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:24 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 162342217500 because target called exit() +Exiting @ tick 145300717500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 9bb344c89..339674edd 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.162342 # Number of seconds simulated -sim_ticks 162342217500 # Number of ticks simulated +sim_seconds 0.145301 # Number of seconds simulated +sim_ticks 145300717500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248957 # Simulator instruction rate (inst/s) -host_tick_rate 71463217 # Simulator tick rate (ticks/s) -host_mem_usage 193608 # Number of bytes of host memory used -host_seconds 2271.69 # Real time elapsed on the host +host_inst_rate 109615 # Simulator instruction rate (inst/s) +host_tick_rate 28162171 # Simulator tick rate (ticks/s) +host_mem_usage 246532 # Number of bytes of host memory used +host_seconds 5159.43 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122220880 # DTB read hits -system.cpu.dtb.read_misses 24742 # DTB read misses +system.cpu.dtb.read_hits 125840781 # DTB read hits +system.cpu.dtb.read_misses 26740 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122245622 # DTB read accesses -system.cpu.dtb.write_hits 40876425 # DTB write hits -system.cpu.dtb.write_misses 28211 # DTB write misses +system.cpu.dtb.read_accesses 125867521 # DTB read accesses +system.cpu.dtb.write_hits 41455603 # DTB write hits +system.cpu.dtb.write_misses 32148 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40904636 # DTB write accesses -system.cpu.dtb.data_hits 163097305 # DTB hits -system.cpu.dtb.data_misses 52953 # DTB misses +system.cpu.dtb.write_accesses 41487751 # DTB write accesses +system.cpu.dtb.data_hits 167296384 # DTB hits +system.cpu.dtb.data_misses 58888 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163150258 # DTB accesses -system.cpu.itb.fetch_hits 65447834 # ITB hits -system.cpu.itb.fetch_misses 37 # ITB misses +system.cpu.dtb.data_accesses 167355272 # DTB accesses +system.cpu.itb.fetch_hits 71694847 # ITB hits +system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65447871 # ITB accesses +system.cpu.itb.fetch_accesses 71694887 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 324684436 # number of cpu cycles simulated +system.cpu.numCycles 290601436 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4119052 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 71175082 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 63645886 # Number of BTB hits +system.cpu.BPredUnit.lookups 82480135 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 75938237 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4123227 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 78114904 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69862682 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 199 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 65447834 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 697103085 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76158972 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65318074 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129743678 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4139889 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 65447834 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1277663 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 324617336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.147461 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.098162 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1959581 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 207 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 74561330 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 742166836 # Number of instructions fetch has processed +system.cpu.fetch.Branches 82480135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71822263 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 139513131 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17330809 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 63439148 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 978 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 71694847 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1192151 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 290532092 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.554509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.199356 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 194873658 60.03% 60.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10240367 3.15% 63.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15840170 4.88% 68.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13915379 4.29% 72.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11968140 3.69% 76.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13832570 4.26% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5877215 1.81% 82.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3421155 1.05% 83.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 54648682 16.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151018961 51.98% 51.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11571435 3.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15893812 5.47% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 16015901 5.51% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13154387 4.53% 71.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15895840 5.47% 76.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6797382 2.34% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3595958 1.24% 80.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56588416 19.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 324617336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.234563 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.147017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 142213399 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 44833716 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122593858 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5374385 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9601978 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4163323 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 844 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 687863087 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3402 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9601978 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 149604933 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12564419 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 695 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 115293181 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 37552130 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 678776451 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 31522766 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 517767610 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 894089158 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 894087193 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1965 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 290532092 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.283826 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.553899 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 90749428 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 49730662 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 127248783 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9786563 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13016656 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4449520 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 730230726 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3285 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 13016656 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 99035242 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12652833 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 552 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 123482350 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42344459 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 716220339 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 269 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32893905 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3996747 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 545787696 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 940589265 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 940587099 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2166 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 53912721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 73444449 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 125962189 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42585734 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11874393 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4773328 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 618660755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 605609121 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 51673321 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 324617336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.865609 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 81932807 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 82656426 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 131826399 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43887979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16660025 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7232836 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 645179442 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 621649928 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 372243 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 78544400 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 43423824 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 290532092 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.139695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.881267 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71097940 24.47% 24.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 58395265 20.10% 44.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 55676712 19.16% 63.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31603347 10.88% 74.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 33236000 11.44% 86.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23958494 8.25% 94.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12196902 4.20% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3766140 1.30% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 601292 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 324617336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290532092 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4587811 88.39% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 54 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 424179 8.17% 96.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 178446 3.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 451150539 72.57% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7830 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 128375845 20.65% 93.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 42115665 6.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 605609121 # Type of FU issued -system.cpu.iq.rate 1.865224 # Inst issue rate -system.cpu.iq.fu_busy_cnt 5929666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 670348766 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10009719 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 621649928 # Type of FU issued +system.cpu.iq.rate 2.139184 # Inst issue rate +system.cpu.iq.fu_busy_cnt 5190490 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008350 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1539391263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 723910400 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 609602063 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3418 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1948 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 626838696 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11620337 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11448147 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 24101 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3134413 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17312357 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 134964 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 365628 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4436658 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6020 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5886 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 50751 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 661873499 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3111469 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42585734 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599183867 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122245685 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6425254 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13016656 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1515186 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 101274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 690779591 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2446688 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 131826399 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43887979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41001 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13794 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 365628 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4028203 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 602481 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4630684 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 613929253 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 125867602 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7720675 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43212719 # number of nop insts executed -system.cpu.iew.exec_refs 163178153 # number of memory reference insts executed -system.cpu.iew.exec_branches 67449018 # Number of branches executed -system.cpu.iew.exec_stores 40932468 # Number of stores executed -system.cpu.iew.exec_rate 1.845435 # Inst execution rate -system.cpu.iew.wb_sent 597097102 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 595948678 # cumulative count of insts written-back -system.cpu.iew.wb_producers 395837342 # num instructions producing a value -system.cpu.iew.wb_consumers 486897348 # num instructions consuming a value +system.cpu.iew.exec_nop 45600120 # number of nop insts executed +system.cpu.iew.exec_refs 167374804 # number of memory reference insts executed +system.cpu.iew.exec_branches 68499674 # Number of branches executed +system.cpu.iew.exec_stores 41507202 # Number of stores executed +system.cpu.iew.exec_rate 2.112616 # Inst execution rate +system.cpu.iew.wb_sent 611080780 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 609603660 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419952220 # num instructions producing a value +system.cpu.iew.wb_consumers 531843575 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.835470 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.812979 # average fanout of values written-back +system.cpu.iew.wb_rate 2.097731 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789616 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 88769206 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 315015358 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.910564 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4122409 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 277515436 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.168733 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.607930 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91720629 33.05% 33.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 75337959 27.15% 60.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31629889 11.40% 71.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9762168 3.52% 75.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10089201 3.64% 78.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21364718 7.70% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5897222 2.13% 88.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2300204 0.83% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29413446 10.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 315015358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 277515436 # Number of insts commited each cycle system.cpu.commit.count 601856963 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed @@ -288,50 +290,50 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20370282 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29413446 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 956313792 # The number of ROB reads -system.cpu.rob.rob_writes 1333072216 # The number of ROB writes -system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 938663770 # The number of ROB reads +system.cpu.rob.rob_writes 1394275800 # The number of ROB writes +system.cpu.timesIdled 2250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 69344 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.574101 # CPI: Total CPI of All Threads -system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 844972523 # number of integer regfile reads -system.cpu.int_regfile_writes 489243634 # number of integer regfile writes -system.cpu.fp_regfile_reads 253 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cpi 0.513836 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.513836 # CPI: Total CPI of All Threads +system.cpu.ipc 1.946145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.946145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 864545189 # number of integer regfile reads +system.cpu.int_regfile_writes 501712619 # number of integer regfile writes +system.cpu.fp_regfile_reads 277 # number of floating regfile reads +system.cpu.fp_regfile_writes 57 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 32 # number of replacements -system.cpu.icache.tagsinuse 774.695980 # Cycle average of tags in use -system.cpu.icache.total_refs 65446683 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 71998.551155 # Average number of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.tagsinuse 798.939045 # Cycle average of tags in use +system.cpu.icache.total_refs 71693570 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 940 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 76269.755319 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.378270 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 65446683 # number of ReadReq hits -system.cpu.icache.demand_hits 65446683 # number of demand (read+write) hits -system.cpu.icache.overall_hits 65446683 # number of overall hits -system.cpu.icache.ReadReq_misses 1151 # number of ReadReq misses -system.cpu.icache.demand_misses 1151 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1151 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 42013000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 42013000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 42013000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 65447834 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 65447834 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 798.939045 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.390107 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 71693570 # number of ReadReq hits +system.cpu.icache.demand_hits 71693570 # number of demand (read+write) hits +system.cpu.icache.overall_hits 71693570 # number of overall hits +system.cpu.icache.ReadReq_misses 1277 # number of ReadReq misses +system.cpu.icache.demand_misses 1277 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1277 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 46025000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 46025000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 46025000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 71694847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 71694847 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 71694847 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36501.303215 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36501.303215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36041.503524 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36041.503524 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36041.503524 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 242 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 242 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 242 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 940 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 940 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 940 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32280000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32280000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32280000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33513000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33513000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33513000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35511.551155 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35652.127660 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35652.127660 # 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Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 111416977 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38165226 # number of WriteReq hits +system.cpu.dcache.replacements 470805 # number of replacements +system.cpu.dcache.tagsinuse 4093.951768 # Cycle average of tags in use +system.cpu.dcache.total_refs 151630549 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 474901 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 319.288755 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126064000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4093.951768 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 113482808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38147738 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 149582203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 149582203 # number of overall hits -system.cpu.dcache.ReadReq_misses 787554 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1286095 # number of WriteReq misses -system.cpu.dcache.demand_misses 2073649 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2073649 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11948365500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 18377052890 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 30325418390 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30325418390 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 112204531 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits 151630546 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 151630546 # number of overall hits +system.cpu.dcache.ReadReq_misses 730789 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1303583 # number of WriteReq misses +system.cpu.dcache.demand_misses 2034372 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2034372 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11799719000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 19632109224 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 31431828224 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 31431828224 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 114213597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 151655852 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.007019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.032600 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013673 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013673 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14624.181040 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 778498 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 153664918 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 153664918 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.006398 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.033043 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.013239 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013239 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16146.547088 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15060.114488 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15450.383816 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15450.383816 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 917496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 119 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7710.050420 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423176 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 569368 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1029147 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1598515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1598515 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256948 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 475134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 475134 # number of overall MSHR misses +system.cpu.dcache.writebacks 423137 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 511918 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1047553 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1559471 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1559471 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 218871 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 256030 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 474901 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 474901 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4510496494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4510496494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1640511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3027783994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4668295494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4668295494 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003133 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003133 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001916 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003090 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003090 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7495.335152 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.895379 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74455 # number of replacements -system.cpu.l2cache.tagsinuse 17721.214963 # Cycle average of tags in use -system.cpu.l2cache.total_refs 477367 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90353 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.283355 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74456 # number of replacements +system.cpu.l2cache.tagsinuse 17669.602101 # Cycle average of tags in use +system.cpu.l2cache.total_refs 478138 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90356 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.291713 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.052925 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487884 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186178 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423176 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 197108 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 383286 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 383286 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32917 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59840 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92757 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92757 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1132170000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2063110500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3195280500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3195280500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219095 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423176 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256948 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 476043 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.150241 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.232888 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194850 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194850 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34394.689674 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.113971 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34447.863773 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1747.606056 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15921.996045 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053333 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485901 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 186860 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 423137 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 196226 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 383086 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 383086 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32951 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92755 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92755 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1133426500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2066052500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3199479000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3199479000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 219811 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 423137 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 256030 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 475841 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 475841 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.149906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.233582 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.194929 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.194929 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34397.332403 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.062069 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34493.870950 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34493.870950 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 468000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 80 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5850 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59322 # number of writebacks +system.cpu.l2cache.writebacks 59325 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32917 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59840 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92757 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92757 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32951 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92755 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1020989500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876396000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2897385500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2897385500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1022116000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877697000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2899813000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2899813000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232888 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.088435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31356.885027 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.194929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.194929 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.271039 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31397.515216 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |