diff options
Diffstat (limited to 'tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 996 |
1 files changed, 498 insertions, 498 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index b2bd08a2b..1e34e6b02 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,530 +1,530 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 210962 # Simulator instruction rate (inst/s) -host_mem_usage 262196 # Number of bytes of host memory used -host_seconds 2855.31 # Real time elapsed on the host -host_tick_rate 66454392 # Simulator tick rate (ticks/s) +sim_seconds 0.189745 # Number of seconds simulated +sim_ticks 189745250000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 602359850 # Number of instructions simulated -sim_seconds 0.189748 # Number of seconds simulated -sim_ticks 189747670000 # Number of ticks simulated -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 74615208 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 80130233 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1670 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3884107 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 80516162 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 86913734 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1397693 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 3943213 # The number of times a branch was mispredicted -system.cpu.commit.branches 70828611 # Number of branches committed -system.cpu.commit.bw_lim_events 15126616 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 602359901 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 6307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 75686006 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 366955970 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.641505 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.022822 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118814632 32.38% 32.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 123407521 33.63% 66.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 52313499 14.26% 80.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12481991 3.40% 83.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 20938472 5.71% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13691845 3.73% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7616390 2.08% 95.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2565004 0.70% 95.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15126616 4.12% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366955970 # Number of insts commited each cycle -system.cpu.commit.count 602359901 # Number of instructions committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.int_insts 533522679 # Number of committed integer instructions. -system.cpu.commit.loads 148952604 # Number of loads committed -system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.refs 219173627 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 602359850 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359850 # Number of Instructions Simulated -system.cpu.cpi 0.630014 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.630014 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1349 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 1334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 152000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.011119 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 15 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 138720806 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13339.905680 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8226.668223 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 138476956 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3252936000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001758 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 243850 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 46844 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1620703000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001420 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 197006 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 1337 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 1337 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 17857.107875 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.095668 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 67921343 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 26717590518 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.021553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1496188 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1248875 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2561939027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 247313 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.596339 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 464.535408 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 9582528 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 208138337 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 17224.064370 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9413.601550 # average overall mshr miss latency -system.cpu.dcache.demand_hits 206398299 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 29970526518 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.008360 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1740038 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1295719 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4182642027 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002135 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 444319 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4094.816119 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999711 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 208138337 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 17224.064370 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9413.601550 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 206398299 # number of overall hits -system.cpu.dcache.overall_miss_latency 29970526518 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.008360 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1740038 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1295719 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4182642027 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002135 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 444319 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 440221 # number of replacements -system.cpu.dcache.sampled_refs 444317 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.816119 # Cycle average of tags in use -system.cpu.dcache.total_refs 206400979 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 88948000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 394697 # number of writebacks -system.cpu.decode.BlockedCycles 57854165 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 1286 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 5859491 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 711052352 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 160285716 # Number of cycles decode is idle -system.cpu.decode.RunCycles 140722772 # Number of cycles decode is running -system.cpu.decode.SquashCycles 11629973 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 4744 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 8093316 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses +host_inst_rate 57706 # Simulator instruction rate (inst/s) +host_tick_rate 18177630 # Simulator tick rate (ticks/s) +host_mem_usage 255472 # Number of bytes of host memory used +host_seconds 10438.39 # Real time elapsed on the host +sim_insts 602359840 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 86913734 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 70195415 # Number of cache lines fetched -system.cpu.fetch.Cycles 151344798 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 922649 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 678928974 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 4471477 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.229025 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 70195415 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 76012901 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.789031 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 378585942 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.910009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.919514 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.numCycles 379490501 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 86928352 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80528545 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3884028 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 80092626 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 74490175 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 1400314 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1695 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 70199329 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 678993278 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86928352 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 75890489 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151223447 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4473449 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 70199329 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 924096 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 378585601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.910199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.920341 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 227241307 60.02% 60.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25123172 6.64% 66.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 17643544 4.66% 71.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 21901113 5.78% 77.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11234102 2.97% 80.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11763660 3.11% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4451384 1.18% 84.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7295384 1.93% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 51932276 13.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 227362317 60.06% 60.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25157685 6.65% 66.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 17486331 4.62% 71.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 21712752 5.74% 77.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11244311 2.97% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11955687 3.16% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4446495 1.17% 84.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7289466 1.93% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 51930557 13.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 378585942 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 378585601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.229066 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.789223 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 160153181 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 58093543 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 140600980 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8092430 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11645467 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 5860940 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1284 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 711110342 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4730 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11645467 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 169808793 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7731895 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 102804 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 138994558 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50302084 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 699378515 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 44454073 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4930432 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 610 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723286205 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3254558347 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3254558219 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 627417450 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 95868750 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6063 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6060 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 83251971 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172882787 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80813690 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 15992884 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23084405 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 678074240 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7046 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 648954836 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 321485 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 74818706 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 185294154 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 741 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 378585601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.714156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.635088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99002495 26.15% 26.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 107489876 28.39% 54.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72418873 19.13% 73.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 48797355 12.89% 86.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22456398 5.93% 92.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 17049752 4.50% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6015477 1.59% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3775065 1.00% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1580310 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 378585601 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 164864 5.19% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2380738 74.98% 80.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 629773 19.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 405017368 62.41% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6545 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 167786137 25.85% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76144783 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 648954836 # Type of FU issued +system.cpu.iq.rate 1.710069 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3175375 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004893 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1679992097 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 753424475 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 636613588 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 652130191 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 25625639 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 23930184 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271058 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 524844 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10592669 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 15888 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12323 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 11645467 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 694588 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 678142321 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3267373 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172882787 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80813690 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5710 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7359 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3854 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 524844 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3752039 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 638545 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4390584 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642328929 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 165615332 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6625907 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 61035 # number of nop insts executed +system.cpu.iew.exec_refs 240294143 # number of memory reference insts executed +system.cpu.iew.exec_branches 74636278 # Number of branches executed +system.cpu.iew.exec_stores 74678811 # Number of stores executed +system.cpu.iew.exec_rate 1.692609 # Inst execution rate +system.cpu.iew.wb_sent 637663585 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 636613604 # cumulative count of insts written-back +system.cpu.iew.wb_producers 410591202 # num instructions producing a value +system.cpu.iew.wb_consumers 620919251 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.677548 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661263 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 602359891 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 75781554 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6305 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3943142 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 366940135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.641575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.021399 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118738354 32.36% 32.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 123466865 33.65% 66.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 52180899 14.22% 80.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12560554 3.42% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20975428 5.72% 89.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13806386 3.76% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7633759 2.08% 95.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2509750 0.68% 95.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15068140 4.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 366940135 # Number of insts commited each cycle +system.cpu.commit.count 602359891 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 219173623 # Number of memory references committed +system.cpu.commit.loads 148952602 # Number of loads committed +system.cpu.commit.membars 1328 # Number of memory barriers committed +system.cpu.commit.branches 70828609 # Number of branches committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.int_insts 533522671 # Number of committed integer instructions. +system.cpu.commit.function_calls 997573 # Number of function calls committed. +system.cpu.commit.bw_lim_events 15068140 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 1030012828 # The number of ROB reads +system.cpu.rob.rob_writes 1367937117 # The number of ROB writes +system.cpu.timesIdled 36799 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 904900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359840 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359840 # Number of Instructions Simulated +system.cpu.cpi 0.630006 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.630006 # CPI: Total CPI of All Threads +system.cpu.ipc 1.587286 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.587286 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3206207435 # number of integer regfile reads +system.cpu.int_regfile_writes 661050575 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 70195415 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35447.995666 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34312.158470 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 70194492 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32718500 # number of ReadReq miss cycles +system.cpu.misc_regfile_reads 912573919 # number of misc regfile reads +system.cpu.misc_regfile_writes 2672 # number of misc regfile writes +system.cpu.icache.replacements 41 # number of replacements +system.cpu.icache.tagsinuse 627.011637 # Cycle average of tags in use +system.cpu.icache.total_refs 70198409 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 729 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 96294.113855 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 627.011637 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.306158 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 70198409 # number of ReadReq hits +system.cpu.icache.demand_hits 70198409 # number of demand (read+write) hits +system.cpu.icache.overall_hits 70198409 # number of overall hits +system.cpu.icache.ReadReq_misses 920 # number of ReadReq misses +system.cpu.icache.demand_misses 920 # number of demand (read+write) misses +system.cpu.icache.overall_misses 920 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 32585000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 32585000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 32585000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 70199329 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 70199329 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 70199329 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 923 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 191 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 25116500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 732 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 96156.838356 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35418.478261 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35418.478261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35418.478261 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 70195415 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35447.995666 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34312.158470 # average overall mshr miss latency -system.cpu.icache.demand_hits 70194492 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32718500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.demand_misses 923 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 191 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25116500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 189 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 189 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 189 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 731 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 731 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 731 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 25045500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25045500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25045500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 732 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 626.402984 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.305861 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 70195415 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35447.995666 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34312.158470 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 70194492 # number of overall hits -system.cpu.icache.overall_miss_latency 32718500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.overall_misses 923 # number of overall misses -system.cpu.icache.overall_mshr_hits 191 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25116500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 732 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 43 # number of replacements -system.cpu.icache.sampled_refs 730 # Sample count of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34261.969904 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 626.402984 # Cycle average of tags in use -system.cpu.icache.total_refs 70194492 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 909399 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 4390377 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 74630961 # Number of branches executed -system.cpu.iew.exec_nop 61033 # number of nop insts executed -system.cpu.iew.exec_rate 1.692381 # Inst execution rate -system.cpu.iew.exec_refs 240248450 # number of memory reference insts executed -system.cpu.iew.exec_stores 74641760 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 692845 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 172870468 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5721 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3255991 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 80793372 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 678046798 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 165606690 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6567715 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 642250536 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 7466 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3846 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 11629973 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 38806 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 12320 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 25624582 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 272347 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 522665 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 15873 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 23917863 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 10572349 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 522665 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 636797 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3753580 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 620419783 # num instructions consuming a value -system.cpu.iew.wb_count 636524370 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.661688 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 410524106 # num instructions producing a value -system.cpu.iew.wb_rate 1.677292 # insts written-back per cycle -system.cpu.iew.wb_sent 637578270 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 3205843747 # number of integer regfile reads -system.cpu.int_regfile_writes 660980878 # number of integer regfile writes -system.cpu.ipc 1.587265 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.587265 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 404976250 62.42% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6544 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 167780307 25.86% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76055147 11.72% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 648818251 # Type of FU issued -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 3420971 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005273 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 164650 4.81% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2528736 73.92% 78.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 727585 21.27% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 652239202 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1679971887 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 636524354 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 753225503 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 677978706 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 648818251 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 7059 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 74717328 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 328508 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 752 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 185330852 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 378585942 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.713794 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.641678 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 99098284 26.18% 26.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 107923682 28.51% 54.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 72401438 19.12% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 48461841 12.80% 86.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21953161 5.80% 92.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16842853 4.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6368110 1.68% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3821983 1.01% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1714590 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 378585942 # Number of insts issued each cycle -system.cpu.iq.rate 1.709687 # Inst issue rate -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 247312 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.062545 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.030776 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 188954 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2003142000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.235969 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58358 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822989000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235969 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58358 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 197735 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34360.710576 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.859290 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 165001 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1124763500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.165545 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32734 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1018296000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165509 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32727 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 440236 # number of replacements +system.cpu.dcache.tagsinuse 4094.816019 # Cycle average of tags in use +system.cpu.dcache.total_refs 206409236 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444332 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 464.538309 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 88952000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.816019 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999711 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 138485254 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67921309 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1329 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1335 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 206406563 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 206406563 # number of overall hits +system.cpu.dcache.ReadReq_misses 243961 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1496222 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 15 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1740183 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1740183 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3253587000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 26715936018 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 152000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 29969523018 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 29969523018 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 138729215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1335 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 208146746 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 208146746 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001759 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.021554 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.011161 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008360 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008360 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13336.504605 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17855.596307 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 17222.052519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 17222.052519 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9582528 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.596339 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 394716 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 46944 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1248905 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 15 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1295849 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1295849 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197017 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247317 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 444334 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 444334 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1620169000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2562065527 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4182234527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4182234527 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.002135 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002135 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8223.498480 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.439614 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 72895 # number of replacements +system.cpu.l2cache.tagsinuse 17837.050931 # Cycle average of tags in use +system.cpu.l2cache.total_refs 420745 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88410 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.759020 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 1909.078024 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15927.972907 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058260 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486083 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165017 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 394716 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_hits 188953 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 353970 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 353970 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32728 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 394697 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 394697 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.758732 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91091 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91091 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1124545500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2003459500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3128005000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3128005000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 197745 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 394716 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247316 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 445061 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 445061 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165506 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235986 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204671 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204671 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34360.348937 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34327.561983 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34339.341977 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34339.341977 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 445047 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34337.872700 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31193.775045 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 353955 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3127905500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.204680 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91092 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2841285000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.204664 # mshr miss rate for demand accesses +system.cpu.l2cache.writebacks 58107 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32722 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses 91085 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 1908.878881 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15928.587231 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058254 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486102 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 445047 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34337.872700 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31193.775045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 353955 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3127905500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.204680 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91092 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2841285000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.204664 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 91085 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72893 # number of replacements -system.cpu.l2cache.sampled_refs 88408 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 1018131500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1823239000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2841370500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2841370500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235986 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204657 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204657 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.586517 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31239.638127 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17837.466112 # Cycle average of tags in use -system.cpu.l2cache.total_refs 420710 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58103 # number of writebacks -system.cpu.memDep0.conflictingLoads 15581715 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 22335111 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 172870468 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80793372 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 912454826 # number of misc regfile reads -system.cpu.misc_regfile_writes 2676 # number of misc regfile writes -system.cpu.numCycles 379495341 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 7724801 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 627417466 # Number of HB maps that are committed -system.cpu.rename.FullRegisterEvents 610 # Number of times there has been no free registers -system.cpu.rename.IQFullEvents 44461884 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 169816321 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 4814649 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 3254253647 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 699315987 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 723227895 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 139243664 # Number of cycles rename is running -system.cpu.rename.SquashCycles 11629973 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 50068276 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 95810424 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 3254253519 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 102907 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 6090 # count of serializing insts renamed -system.cpu.rename.skidInsts 82758432 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 6087 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 1029874649 # The number of ROB reads -system.cpu.rob.rob_writes 1367730511 # The number of ROB writes -system.cpu.timesIdled 36653 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |