diff options
Diffstat (limited to 'tests/long/00.gzip/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini | 2 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/arm/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 334 |
3 files changed, 172 insertions, 172 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index d12448d3c..07f2d92be 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -498,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/alisai01/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 0ab77604f..facf2b9b0 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2011 17:47:57 -M5 started Mar 30 2011 17:54:33 -M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing +M5 compiled Apr 19 2011 12:47:10 +M5 started Apr 19 2011 12:47:12 +M5 executing on maize +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index a5940d4c5..5fb65989e 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 238408 # Simulator instruction rate (inst/s) -host_mem_usage 258640 # Number of bytes of host memory used -host_seconds 2526.59 # Real time elapsed on the host -host_tick_rate 77778012 # Simulator tick rate (ticks/s) +host_inst_rate 283332 # Simulator instruction rate (inst/s) +host_mem_usage 214996 # Number of bytes of host memory used +host_seconds 2125.99 # Real time elapsed on the host +host_tick_rate 92433779 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 602359865 # Number of instructions simulated sim_seconds 0.196513 # Number of seconds simulated @@ -16,38 +16,38 @@ system.cpu.BPredUnit.condIncorrect 3832102 # Nu system.cpu.BPredUnit.condPredicted 81880205 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 88398894 # Number of BP lookups system.cpu.BPredUnit.usedRAS 1393010 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 70828614 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7897771 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 379244728 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.588315 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 379244728 # Number of insts commited each cycle -system.cpu.commit.COM:count 602359916 # Number of instructions committed -system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 997573 # Number of function calls committed. -system.cpu.commit.COM:int_insts 533522691 # Number of committed integer instructions. -system.cpu.commit.COM:loads 148952607 # Number of loads committed -system.cpu.commit.COM:membars 1328 # Number of memory barriers committed -system.cpu.commit.COM:refs 219173633 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 3891220 # The number of times a branch was mispredicted +system.cpu.commit.branches 70828614 # Number of branches committed +system.cpu.commit.bw_lim_events 7897771 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.commitCommittedInsts 602359916 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 6310 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 86859726 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 379244728 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.588315 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 379244728 # Number of insts commited each cycle +system.cpu.commit.count 602359916 # Number of instructions committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.function_calls 997573 # Number of function calls committed. +system.cpu.commit.int_insts 533522691 # Number of committed integer instructions. +system.cpu.commit.loads 148952607 # Number of loads committed +system.cpu.commit.membars 1328 # Number of memory barriers committed +system.cpu.commit.refs 219173633 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.committedInsts 602359865 # Number of Instructions Simulated system.cpu.committedInsts_total 602359865 # Number of Instructions Simulated system.cpu.cpi 0.652478 # CPI: Cycles Per Instruction @@ -105,8 +105,8 @@ system.cpu.dcache.demand_mshr_misses 443820 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999719 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 4094.849519 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses 208812765 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 17229.974009 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency @@ -128,15 +128,15 @@ system.cpu.dcache.tagsinuse 4094.849519 # Cy system.cpu.dcache.total_refs 207082021 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 89315000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 394264 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 64227537 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 1274 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 5983982 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 722350979 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 163737957 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 138388023 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 12871984 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 4747 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 12891210 # Number of cycles decode is unblocking +system.cpu.decode.BlockedCycles 64227537 # Number of cycles decode is blocked +system.cpu.decode.BranchMispred 1274 # Number of times decode detected a branch misprediction +system.cpu.decode.BranchResolved 5983982 # Number of times decode resolved a branch +system.cpu.decode.DecodedInsts 722350979 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 163737957 # Number of cycles decode is idle +system.cpu.decode.RunCycles 138388023 # Number of cycles decode is running +system.cpu.decode.SquashCycles 12871984 # Number of cycles decode is squashing +system.cpu.decode.SquashedInsts 4747 # Number of squashed instructions handled by decode +system.cpu.decode.UnblockCycles 12891210 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -220,8 +220,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.307172 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 629.087764 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.307172 # Average percentage of cache occupancy system.cpu.icache.overall_accesses 71395519 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35429.359823 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency @@ -244,21 +244,13 @@ system.cpu.icache.total_refs 71394613 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 909571 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 73704412 # Number of branches executed -system.cpu.iew.EXEC:nop 61098 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.622472 # Inst execution rate -system.cpu.iew.EXEC:refs 239165331 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 73423365 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 736448308 # num instructions consuming a value -system.cpu.iew.WB:count 631945179 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.594878 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 438096934 # num instructions producing a value -system.cpu.iew.WB:rate 1.607895 # insts written-back per cycle -system.cpu.iew.WB:sent 632881856 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 4305441 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 73704412 # Number of branches executed +system.cpu.iew.exec_nop 61098 # number of nop insts executed +system.cpu.iew.exec_rate 1.622472 # Inst execution rate +system.cpu.iew.exec_refs 239165331 # number of memory reference insts executed +system.cpu.iew.exec_stores 73423365 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 811047 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 176106355 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 5819 # Number of dispatched non-speculative instructions @@ -286,103 +278,93 @@ system.cpu.iew.lsq.thread.0.squashedStores 11966835 # system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 736448308 # num instructions consuming a value +system.cpu.iew.wb_count 631945179 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.594878 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 438096934 # num instructions producing a value +system.cpu.iew.wb_rate 1.607895 # insts written-back per cycle +system.cpu.iew.wb_sent 632881856 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 1724767298 # number of integer regfile reads system.cpu.int_regfile_writes 495432851 # number of integer regfile writes system.cpu.ipc 1.532620 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.532620 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 643808145 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 3945011 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 392116711 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.641879 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 392116711 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.638079 # Inst issue rate +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 643808145 # Type of FU issued system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fu_busy_cnt 3945011 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 647753136 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 1684034505 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 631945163 # Number of integer instruction queue wakeup accesses @@ -394,6 +376,24 @@ system.cpu.iq.iqSquashedInstsExamined 86496318 # Nu system.cpu.iq.iqSquashedInstsIssued 356529 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 850 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 162226931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.issued_per_cycle::samples 392116711 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.641879 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392116711 # Number of insts issued each cycle +system.cpu.iq.rate 1.638079 # Inst issue rate system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -468,10 +468,10 @@ system.cpu.l2cache.demand_mshr_misses 91150 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.057260 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.487109 # Average percentage of cache occupancy system.cpu.l2cache.occ_blocks::0 1876.282231 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15961.603623 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057260 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487109 # Average percentage of cache occupancy system.cpu.l2cache.overall_accesses 444538 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34340.043442 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency @@ -502,27 +502,27 @@ system.cpu.misc_regfile_writes 2682 # nu system.cpu.numCycles 393026282 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 9628088 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 471021820 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 50048668 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 176696020 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 2034394520 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 711291370 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 553214444 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 138291459 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 12871984 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 54521168 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 82192621 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2034394424 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 107992 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 6480 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 91409775 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6477 # count of temporary serializing insts renamed +system.cpu.rename.BlockCycles 9628088 # Number of cycles rename is blocking +system.cpu.rename.CommittedMaps 471021820 # Number of HB maps that are committed +system.cpu.rename.IQFullEvents 50048668 # Number of times rename has blocked due to IQ full +system.cpu.rename.IdleCycles 176696020 # Number of cycles rename is idle +system.cpu.rename.LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenameLookups 2034394520 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedInsts 711291370 # Number of instructions processed by rename +system.cpu.rename.RenamedOperands 553214444 # Number of destination operands rename has renamed +system.cpu.rename.RunCycles 138291459 # Number of cycles rename is running +system.cpu.rename.SquashCycles 12871984 # Number of cycles rename is squashing +system.cpu.rename.UnblockCycles 54521168 # Number of cycles rename is unblocking +system.cpu.rename.UndoneMaps 82192621 # Number of HB maps that are undone due to squashing +system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 2034394424 # Number of integer rename lookups +system.cpu.rename.serializeStallCycles 107992 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializingInsts 6480 # count of serializing insts renamed +system.cpu.rename.skidInsts 91409775 # count of insts added to the skid buffer +system.cpu.rename.tempSerializingInsts 6477 # count of temporary serializing insts renamed system.cpu.rob.rob_reads 1060565987 # The number of ROB reads system.cpu.rob.rob_writes 1391311417 # The number of ROB writes system.cpu.timesIdled 36947 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 48 # Number of system calls +system.cpu.workload.num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- |