diff options
Diffstat (limited to 'tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt | 181 |
1 files changed, 91 insertions, 90 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index bd7d26f79..4b4cf244a 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1674821 # Simulator instruction rate (inst/s) -host_mem_usage 210020 # Number of bytes of host memory used -host_seconds 357.42 # Real time elapsed on the host -host_tick_rate 2260963263 # Simulator tick rate (ticks/s) +host_inst_rate 1492183 # Simulator instruction rate (inst/s) +host_mem_usage 211112 # Number of bytes of host memory used +host_seconds 401.17 # Real time elapsed on the host +host_tick_rate 2012902303 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 598619824 # Number of instructions simulated -sim_seconds 0.808121 # Number of seconds simulated -sim_ticks 808121048000 # Number of ticks simulated +sim_seconds 0.807517 # Number of seconds simulated +sim_ticks 807517408000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21168.913260 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18168.913260 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21105.418688 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18105.418688 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4018770000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4006716000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3449241000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3437187000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 69110224 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17283504000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.004446 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 308634 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16357602000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004446 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 308634 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 54322.323841 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51322.323841 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 69111608 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 16690534000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.004426 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 307250 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 15768784000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.004426 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 307250 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42734.717951 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency -system.cpu.dcache.demand_hits 216713991 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21302274000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002295 # miss rate for demand accesses -system.cpu.dcache.demand_misses 498477 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 41636.575047 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency +system.cpu.dcache.demand_hits 216715375 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 20697250000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002289 # miss rate for demand accesses +system.cpu.dcache.demand_misses 497093 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 19806843000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002295 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 498477 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 19205971000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002289 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 497093 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999571 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.243213 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999572 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.246847 # Average occupied blocks per context system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42734.717951 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 41636.575047 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 216713991 # number of overall hits -system.cpu.dcache.overall_miss_latency 21302274000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002295 # miss rate for overall accesses -system.cpu.dcache.overall_misses 498477 # number of overall misses +system.cpu.dcache.overall_hits 216715375 # number of overall hits +system.cpu.dcache.overall_miss_latency 20697250000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002289 # miss rate for overall accesses +system.cpu.dcache.overall_misses 497093 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 19806843000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002295 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 498477 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 19205971000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002289 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 497093 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 433495 # number of replacements system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.243213 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.246847 # Cycle average of tags in use system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 537993000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 305427 # number of writebacks +system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 305501 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 643 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.282040 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 577.617873 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.282055 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 577.648910 # Average occupied blocks per context system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 12 # number of replacements system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 577.617873 # Cycle average of tags in use +system.cpu.icache.tagsinuse 577.648910 # Cycle average of tags in use system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,36 +150,37 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 12882896000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9909920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247748 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 12273 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 12244700000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.950462 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 235475 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9419000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950462 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 235475 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 157466 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1717040000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173346 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33020 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1320800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173346 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33020 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 60886 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits 157753 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1702116000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.171839 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32733 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1309320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32733 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59502 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3166072000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 3094104000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 60886 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2435440000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 59502 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2380080000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 60886 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 305427 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 305427 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 59502 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 305501 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 305501 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.359132 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.379196 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 157466 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14599936000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.640681 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 280768 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 170026 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 13946816000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.612020 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 268208 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11230720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.640681 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 280768 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 10728320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.612020 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 268208 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.049205 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.452726 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1612.352730 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14834.915268 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.050080 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.453180 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1641.035711 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14849.786647 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 157466 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14599936000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.640681 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 280768 # number of overall misses +system.cpu.l2cache.overall_hits 170026 # number of overall hits +system.cpu.l2cache.overall_miss_latency 13946816000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.612020 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 268208 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11230720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.640681 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 280768 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 10728320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.612020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 268208 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 81265 # number of replacements -system.cpu.l2cache.sampled_refs 96683 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 80841 # number of replacements +system.cpu.l2cache.sampled_refs 96272 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16447.267999 # Cycle average of tags in use -system.cpu.l2cache.total_refs 324771 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16490.822357 # Cycle average of tags in use +system.cpu.l2cache.total_refs 325322 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61092 # number of writebacks +system.cpu.l2cache.writebacks 60805 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1616242096 # number of cpu cycles simulated +system.cpu.numCycles 1615034816 # number of cpu cycles simulated system.cpu.num_insts 598619824 # Number of instructions executed system.cpu.num_refs 219174038 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls |