diff options
Diffstat (limited to 'tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 64 |
1 files changed, 33 insertions, 31 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 1bd86bd33..a8a069318 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,25 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 182414509 # Number of BTB hits -global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted -global.BPredUnit.lookups 254458067 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 104414 # Simulator instruction rate (inst/s) -host_mem_usage 206176 # Number of bytes of host memory used -host_seconds 13461.92 # Real time elapsed on the host -host_tick_rate 81909485 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. +host_inst_rate 148318 # Simulator instruction rate (inst/s) +host_mem_usage 208044 # Number of bytes of host memory used +host_seconds 9477.08 # Real time elapsed on the host +host_tick_rate 116350072 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618365 # Number of instructions simulated sim_seconds 1.102659 # Number of seconds simulated sim_ticks 1102659164000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 182414509 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 203429504 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 254458067 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits @@ -291,21 +287,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1083882017 4918.21% - 1 586425796 2660.96% - 2 298714416 1355.44% - 3 164995052 748.68% - 4 47215795 214.25% - 5 14943133 67.81% - 6 6716024 30.47% - 7 790185 3.59% - 8 132701 0.60% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 2203815119 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083882017 49.18% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425796 26.61% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714416 13.55% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995052 7.49% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215795 2.14% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943133 0.68% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716024 0.30% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 790185 0.04% +system.cpu.iq.ISSUE:issued_per_cycle::8 132701 0.01% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 2203815119 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued @@ -387,6 +385,10 @@ system.cpu.l2cache.tagsinuse 16402.911294 # Cy system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61945 # number of writebacks +system.cpu.memDep0.conflictingLoads 460341314 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 141106006 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 301399355 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 2205318329 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed |