diff options
Diffstat (limited to 'tests/long/00.gzip/ref/sparc/linux/o3-timing')
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini | 150 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 48 |
3 files changed, 187 insertions, 21 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 659cb8ca7..02ce84b2d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -136,8 +136,8 @@ size=64 [system.cpu.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc @@ -231,41 +231,167 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList +opList=system.cpu.fuPool.FUList6.opList -[system.cpu.fuPool.FUList5.opList] +[system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList6] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 -[system.cpu.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList7] +[system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList +opList=system.cpu.fuPool.FUList8.opList -[system.cpu.fuPool.FUList7.opList] +[system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess @@ -353,7 +479,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 6ef53b4dd..5c19a7469 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 26 2010 21:00:10 -M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase -M5 started Sep 26 2010 21:05:23 -M5 executing on burrito -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +M5 compiled Nov 15 2010 00:04:22 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 15 2010 00:10:23 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 5cdef52fc..71e9bfc2c 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 119996 # Simulator instruction rate (inst/s) -host_mem_usage 230000 # Number of bytes of host memory used -host_seconds 11713.80 # Real time elapsed on the host -host_tick_rate 51345807 # Simulator tick rate (ticks/s) +host_inst_rate 179682 # Simulator instruction rate (inst/s) +host_mem_usage 208000 # Number of bytes of host memory used +host_seconds 7822.74 # Real time elapsed on the host +host_tick_rate 76885423 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.601455 # Number of seconds simulated @@ -270,6 +270,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.87% # Ty system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemRead 423845666 28.60% 88.48% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 170779885 11.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -287,6 +307,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.00% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemRead 2529934 77.96% 89.96% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemWrite 325689 10.04% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available |