diff options
Diffstat (limited to 'tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt | 166 |
1 files changed, 83 insertions, 83 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 4187ba610..7a3645f45 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2062336 # Simulator instruction rate (inst/s) -host_mem_usage 183952 # Number of bytes of host memory used -host_seconds 722.25 # Real time elapsed on the host -host_tick_rate 2867275090 # Simulator tick rate (ticks/s) +host_inst_rate 2112807 # Simulator instruction rate (inst/s) +host_mem_usage 183960 # Number of bytes of host memory used +host_seconds 704.99 # Real time elapsed on the host +host_tick_rate 2937444703 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514761 # Number of instructions simulated -sim_seconds 2.070880 # Number of seconds simulated -sim_ticks 2070879986000 # Number of ticks simulated +sim_seconds 2.070879 # Number of seconds simulated +sim_ticks 2070879278000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4495936000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 23237.386607 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.386607 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4495621000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4108976000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 4108691000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency @@ -31,47 +31,47 @@ system.cpu.dcache.SwapReq_mshr_misses 40 # nu system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166527019 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7990575000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_hits 166527036 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7990150000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 319623 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7351329000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 319606 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7350938000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 319623 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 319606 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1255.282200 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24335.291355 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568845227 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12486511000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 24335.366840 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22335.366840 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 12485771000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses -system.cpu.dcache.demand_misses 513103 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 11460305000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 11459629000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 513103 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24335.291355 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 24335.366840 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22335.366840 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568845227 # number of overall hits -system.cpu.dcache.overall_miss_latency 12486511000 # number of overall miss cycles +system.cpu.dcache.overall_hits 568845259 # number of overall hits +system.cpu.dcache.overall_miss_latency 12485771000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses -system.cpu.dcache.overall_misses 513103 # number of overall misses +system.cpu.dcache.overall_misses 513071 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 11460305000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 11459629000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 513103 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -83,13 +83,13 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 449136 # number of replacements -system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 449114 # number of replacements +system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.519446 # Cycle average of tags in use -system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 358580000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316447 # number of writebacks +system.cpu.dcache.tagsinuse 4095.519523 # Cycle average of tags in use +system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 358652000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316430 # number of writebacks system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency @@ -148,78 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.566024 # Cycle average of tags in use +system.cpu.icache.tagsinuse 891.565977 # Cycle average of tags in use system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 259752 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 259745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5714544000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 5714390000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 259752 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857272000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 259745 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857195000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 259752 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 194578 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 259745 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 28424 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3655388000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.853920 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 166154 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1827694000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853920 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 166154 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59911 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits 28419 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3655168000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.853934 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 166144 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1827584000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853934 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 166144 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1318042000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1317822000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59911 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 659021000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59911 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_mshr_misses 59901 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316430 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 316447 # number of Writeback misses +system.cpu.l2cache.Writeback_misses 316430 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 316447 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_mshr_misses 316430 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.182232 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.181781 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 28424 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9369932000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.937438 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 425906 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 28419 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9369558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.937446 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 425889 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4684966000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.937438 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 425906 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4684779000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.937446 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 425889 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 454330 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 454308 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 28424 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9369932000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.937438 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 425906 # number of overall misses +system.cpu.l2cache.overall_hits 28419 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9369558000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.937446 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 425889 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4684966000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.937438 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 425906 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4684779000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.937446 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 425889 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -231,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 18201 # number of replacements -system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 18200 # number of replacements +system.cpu.l2cache.sampled_refs 19573 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8449.165713 # Cycle average of tags in use -system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8449.130406 # Cycle average of tags in use +system.cpu.l2cache.total_refs 62277 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4141759972 # number of cpu cycles simulated +system.cpu.numCycles 4141758556 # number of cpu cycles simulated system.cpu.num_insts 1489514761 # Number of instructions executed system.cpu.num_refs 569364430 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls |