diff options
Diffstat (limited to 'tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 2bdd6d4c0..72665606e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1263053 # Simulator instruction rate (inst/s) -host_mem_usage 205412 # Number of bytes of host memory used -host_seconds 1179.30 # Real time elapsed on the host -host_tick_rate 1760361196 # Simulator tick rate (ticks/s) +host_inst_rate 2042056 # Simulator instruction rate (inst/s) +host_mem_usage 207148 # Number of bytes of host memory used +host_seconds 729.42 # Real time elapsed on the host +host_tick_rate 2846083906 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.076001 # Number of seconds simulated @@ -38,13 +38,13 @@ system.cpu.dcache.WriteReq_misses 319595 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency @@ -63,7 +63,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568846579 # number of overall hits system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses @@ -91,13 +91,13 @@ system.cpu.icache.ReadReq_misses 1107 # nu system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency @@ -116,7 +116,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1485111905 # number of overall hits system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses @@ -165,13 +165,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -190,7 +190,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 160849 # number of overall hits system.cpu.l2cache.overall_miss_latency 15260908000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.645963 # miss rate for overall accesses |