diff options
Diffstat (limited to 'tests/long/00.gzip/ref/sparc/linux/simple-timing')
3 files changed, 99 insertions, 110 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 9514e3ea7..9772b8626 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 833f1cfc2..78e3d8264 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:04:04 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 16:28:00 +M5 executing on phenom command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -45,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2075400743000 because target called exit() +Exiting @ tick 2064258667000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 736d779d0..04e7c144d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1385286 # Simulator instruction rate (inst/s) -host_mem_usage 211532 # Number of bytes of host memory used -host_seconds 1075.25 # Real time elapsed on the host -host_tick_rate 1930162951 # Simulator tick rate (ticks/s) +host_inst_rate 1333935 # Simulator instruction rate (inst/s) +host_mem_usage 197236 # Number of bytes of host memory used +host_seconds 1116.64 # Real time elapsed on the host +host_tick_rate 1848636408 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated -sim_seconds 2.075401 # Number of seconds simulated -sim_ticks 2075400743000 # Number of ticks simulated +sim_seconds 2.064259 # Number of seconds simulated +sim_ticks 2064258667000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21012.879485 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18012.879485 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4065698000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4019834000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3485240000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3439376000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1008000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 954000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 392000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 371000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 54403.143945 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51403.143945 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166528617 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17311026000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001907 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 318199 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16356429000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 318199 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166587088 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6156948000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 259728 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5377764000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 259728 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. @@ -47,42 +47,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 41777.116781 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568847975 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21376724000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000899 # miss rate for demand accesses -system.cpu.dcache.demand_misses 511685 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 22454.694692 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568906446 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10176782000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses +system.cpu.dcache.demand_misses 453214 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 19841669000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000899 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 511685 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8817140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 453214 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999812 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.231029 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999811 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 41777.116781 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568847975 # number of overall hits -system.cpu.dcache.overall_miss_latency 21376724000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000899 # miss rate for overall accesses -system.cpu.dcache.overall_misses 511685 # number of overall misses +system.cpu.dcache.overall_hits 568906446 # number of overall hits +system.cpu.dcache.overall_miss_latency 10176782000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses +system.cpu.dcache.overall_misses 453214 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 19841669000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000899 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 511685 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.231029 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 567036000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316439 # number of writebacks +system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 407009 # number of writebacks system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 1107 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.442593 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 906.429761 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.442603 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency @@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 118 # number of replacements system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 906.429761 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -142,37 +142,28 @@ system.cpu.idle_fraction 0 # Pe system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12098 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12877124000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.953422 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247637 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9905480000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.953422 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247637 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 199710 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3121300000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.231101 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 60025 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2401000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.231101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 60025 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 161183 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1737320000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.171692 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1336400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171692 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33410 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 58482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.221675 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3040960000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 58482 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2339280000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 58482 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316439 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316439 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 162275 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1680536000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.166080 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32318 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1292720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166080 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32318 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 407009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 407009 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.448937 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -181,44 +172,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 173281 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14614444000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.618599 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 281047 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 361985 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4801836000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.203252 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 92343 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11241880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.618599 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 281047 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3693720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.203252 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 92343 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052996 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.447533 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1736.572582 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14664.762880 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.057187 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.483685 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 173281 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14614444000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.618599 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 281047 # number of overall misses +system.cpu.l2cache.overall_hits 361985 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4801836000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.203252 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 92343 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11241880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.618599 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 281047 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3693720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.203252 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 92343 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 82461 # number of replacements -system.cpu.l2cache.sampled_refs 97909 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 74112 # number of replacements +system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16401.335462 # Cycle average of tags in use -system.cpu.l2cache.total_refs 337682 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use +system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61551 # number of writebacks +system.cpu.l2cache.writebacks 59035 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4150801486 # number of cpu cycles simulated +system.cpu.numCycles 4128517334 # number of cpu cycles simulated system.cpu.num_insts 1489523295 # Number of instructions executed system.cpu.num_refs 569365767 # Number of memory references system.cpu.workload.PROG:num_syscalls 49 # Number of system calls |