diff options
Diffstat (limited to 'tests/long/00.gzip/ref/sparc/linux')
15 files changed, 541 insertions, 582 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 857d77efe..ee1f88977 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -22,6 +22,7 @@ SSITSize=1024 activity=0 backComSize=5 cachePorts=200 +checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -36,6 +37,8 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 @@ -104,16 +107,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -122,8 +123,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -281,16 +280,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -299,8 +296,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -321,16 +316,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -339,8 +332,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -368,6 +359,7 @@ cmd=gzip input.log 1 cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 @@ -376,6 +368,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -392,7 +385,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 8ee292d5b..293987f44 100644..100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:45 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1102714100000 because target called exit() +Exiting @ tick 1102659088000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index a32e8681e..3e5a615cf 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,438 +1,414 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 181883102 # Number of BTB hits -global.BPredUnit.BTBLookups 205056000 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 84375502 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 253548806 # Number of conditional branches predicted -global.BPredUnit.lookups 253548806 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 116576 # Simulator instruction rate (inst/s) -host_mem_usage 226608 # Number of bytes of host memory used -host_seconds 12057.44 # Real time elapsed on the host -host_tick_rate 91455071 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 445533165 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 138523488 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 741821167 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 303434180 # Number of stores inserted to the mem dependence unit. +host_inst_rate 159348 # Simulator instruction rate (inst/s) +host_mem_usage 206344 # Number of bytes of host memory used +host_seconds 8821.04 # Real time elapsed on the host +host_tick_rate 125003315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405610550 # Number of instructions simulated -sim_seconds 1.102714 # Number of seconds simulated -sim_ticks 1102714100000 # Number of ticks simulated -system.cpu.commit.COM:branches 86246390 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8144258 # number cycles where commit BW limit reached +sim_insts 1405618365 # Number of instructions simulated +sim_seconds 1.102659 # Number of seconds simulated +sim_ticks 1102659088000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 182414509 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 203429498 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 254458061 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 254458061 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 86248929 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 8096109 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1965947566 +system.cpu.commit.COM:committed_per_cycle.samples 1964055004 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1089819992 5543.48% - 1 575192807 2925.78% - 2 120683737 613.87% - 3 121997081 620.55% - 4 27903521 141.93% - 5 7399306 37.64% - 6 10435277 53.08% - 7 4371587 22.24% - 8 8144258 41.43% + 0 1088074201 5539.94% + 1 575643784 2930.89% + 2 120435541 613.20% + 3 120975798 615.95% + 4 27955067 142.33% + 5 8084166 41.16% + 6 10447088 53.19% + 7 4343250 22.11% + 8 8096109 41.22% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 1489528973 # Number of instructions committed -system.cpu.commit.COM:loads 402516086 # Number of loads committed +system.cpu.commit.COM:count 1489537508 # Number of instructions committed +system.cpu.commit.COM:loads 402517243 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569373868 # Number of memory references committed +system.cpu.commit.COM:refs 569375199 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 84375502 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1379622895 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405610550 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated -system.cpu.cpi 1.569018 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.569018 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 430903803 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21506.820895 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.823732 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 430676780 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4882543000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000527 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 227023 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 610037 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 676261500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000527 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses +system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1390237652 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405618365 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated +system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14297.662769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.135084 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 425346235 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 13092355500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 915699 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 667386 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1685830500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 6037.500000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 361500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 165064291 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 64362.786896 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.204206 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164722312 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22010721500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002072 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 341979 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1792165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2651775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002072 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 341979 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 37763.269313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.327068 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 83930150000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12696288000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1192.736607 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1119.158447 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 595968094 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 47263.919107 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency -system.cpu.dcache.demand_hits 595399092 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26893264500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000955 # miss rate for demand accesses -system.cpu.dcache.demand_misses 569002 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2402202 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3328036500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000955 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 569002 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30916.284897 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency +system.cpu.dcache.demand_hits 589980331 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 97022505500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3138233 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2538011 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 14382118500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 595968094 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 47263.919107 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30916.284897 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 595399092 # number of overall hits -system.cpu.dcache.overall_miss_latency 26893264500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000955 # miss rate for overall accesses -system.cpu.dcache.overall_misses 569002 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2402202 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3328036500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000955 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 569002 # number of overall MSHR misses +system.cpu.dcache.overall_hits 589980331 # number of overall hits +system.cpu.dcache.overall_miss_latency 97022505500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3138233 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2538011 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 14382118500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 495151 # number of replacements -system.cpu.dcache.sampled_refs 499247 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 523278 # number of replacements +system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.753267 # Cycle average of tags in use -system.cpu.dcache.total_refs 595470173 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 85544000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338813 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 411958316 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3446272352 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 768408181 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 782722330 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239479384 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2858739 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 253548806 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 356679455 # Number of cache lines fetched -system.cpu.fetch.Cycles 1203440686 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10248277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3739797008 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 90313792 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.114966 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 356679455 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 181883102 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.695724 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use +system.cpu.dcache.total_refs 590215067 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 348749 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 416443317 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3435538799 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 762668513 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 782001789 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239759977 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2941385 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 254458061 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 354588619 # Number of cache lines fetched +system.cpu.fetch.Cycles 1199300749 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10659931 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3732201000 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 354588619 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2205426950 +system.cpu.fetch.rateDist.samples 2203814981 system.cpu.fetch.rateDist.min_value 0 - 0 1358665764 6160.56% - 1 256941668 1165.04% - 2 81115553 367.80% - 3 38329197 173.79% - 4 87812032 398.16% - 5 41184299 186.74% - 6 30948569 140.33% - 7 20663338 93.69% - 8 289766530 1313.88% + 0 1359102894 6167.05% + 1 256500547 1163.89% + 2 81150170 368.23% + 3 38425919 174.36% + 4 85384463 387.44% + 5 41200023 186.95% + 6 32567288 147.78% + 7 20688755 93.88% + 8 288794922 1310.43% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 356679310 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9956.762749 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6465.262380 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 356677957 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13471500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1353 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 8747500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 354588619 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 354586492 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1353 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 263620.071693 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 257319.660377 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 356679310 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9956.762749 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency -system.cpu.icache.demand_hits 356677957 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13471500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1353 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 8747500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 354588619 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency +system.cpu.icache.demand_hits 354586492 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1353 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 356679310 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9956.762749 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency +system.cpu.icache.overall_accesses 354588619 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 356677957 # number of overall hits -system.cpu.icache.overall_miss_latency 13471500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1353 # number of overall misses -system.cpu.icache.overall_mshr_hits 145 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 8747500 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 354586492 # number of overall hits +system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_misses 2127 # number of overall misses +system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1353 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 208 # number of replacements -system.cpu.icache.sampled_refs 1353 # Sample count of references to valid blocks. +system.cpu.icache.replacements 222 # number of replacements +system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1040.462476 # Cycle average of tags in use -system.cpu.icache.total_refs 356677957 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1057.993144 # Cycle average of tags in use +system.cpu.icache.total_refs 354586492 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1251 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 127605912 # Number of branches executed -system.cpu.iew.EXEC:nop 350340512 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.854314 # Inst execution rate -system.cpu.iew.EXEC:refs 751911003 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 205327510 # Number of stores executed +system.cpu.idleCycles 1503196 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 128154505 # Number of branches executed +system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate +system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 207432555 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1480058841 # num instructions consuming a value -system.cpu.iew.WB:count 1846013592 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.961975 # average fanout of values written-back +system.cpu.iew.WB:consumers 1490113215 # num instructions consuming a value +system.cpu.iew.WB:count 1862924801 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1423779046 # num instructions producing a value -system.cpu.iew.WB:rate 0.837032 # insts written-back per cycle -system.cpu.iew.WB:sent 1859125771 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 92169328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 589466 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 741821167 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21373722 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17131490 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 303434180 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2869215575 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 546583493 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 102562223 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1884127631 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 34476 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1435567297 # num instructions producing a value +system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle +system.cpu.iew.WB:sent 1872447487 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 91815044 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3100855 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21390967 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17059392 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 301399339 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2879831174 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94512444 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1894795217 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6237 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239479384 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 64949 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9892 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239759977 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75722 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115050739 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 46193 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6187227 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 339305081 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 136576398 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6187227 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1512324 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90657004 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.637341 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.637341 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1986689854 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 134541383 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 90333500 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1989307661 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1179867838 59.39% # Type of FU issued + IntAlu 1186637129 59.65% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 3034528 0.15% # Type of FU issued + FloatAdd 2990803 0.15% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 573302529 28.86% # Type of FU issued - MemWrite 230484959 11.60% # Type of FU issued + MemRead 571681967 28.74% # Type of FU issued + MemWrite 227997762 11.46% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3941211 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.001984 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 4014627 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 143231 3.63% # attempts to use FU when none available + IntAlu 142220 3.54% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 224126 5.69% # attempts to use FU when none available + FloatAdd 232755 5.80% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3231195 81.98% # attempts to use FU when none available - MemWrite 342659 8.69% # attempts to use FU when none available + MemRead 3328922 82.92% # attempts to use FU when none available + MemWrite 310730 7.74% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2205426950 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1088269781 4934.51% - 1 585554812 2655.06% - 2 294018661 1333.16% - 3 167298864 758.58% - 4 47518780 215.46% - 5 16542191 75.01% - 6 5287334 23.97% - 7 801167 3.63% - 8 135360 0.61% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 0.900818 # Inst issue rate -system.cpu.iq.iqInstsAdded 2497204504 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1986689854 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21670559 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1069656656 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 613177 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19427058 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1294993594 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 272224 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5810.711032 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.711032 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1581815000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::samples 2203814981 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083881876 49.18% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425801 26.61% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714420 13.55% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995038 7.49% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215803 2.14% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943143 0.68% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716019 0.30% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 790183 0.04% +system.cpu.iq.ISSUE:issued_per_cycle::8 132698 0.01% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 2203814981 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 +system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate +system.cpu.iq.iqInstsAdded 2506731488 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1989307661 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21683045 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1079315429 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 646014 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19439374 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1293054156 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.562838 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.514866 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9570275000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 272224 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 765143000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 272224 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 228376 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5108.225294 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.225294 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 193435 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 178486500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.152998 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34941 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 73663500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.152998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34941 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 69802 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.366465 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.524054 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 363694000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34106.857257 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384760 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 214678 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1194217500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.140229 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35014 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1085517500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140229 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35014 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 69802 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154299000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 69802 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338813 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 338813 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 348749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 348749 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.927611 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.234507 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 500600 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5730.801035 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 193435 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1760301500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.613594 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 307165 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34273.636870 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 214678 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10764492500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.593992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 314075 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 838806500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.613594 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 307165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9781481000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.593992 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 314075 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 500600 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5730.801035 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34273.636870 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 193435 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1760301500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.613594 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 307165 # number of overall misses +system.cpu.l2cache.overall_hits 214678 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10764492500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.593992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 314075 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 838806500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.613594 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 307165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9781481000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.593992 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 314075 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 84439 # number of replacements -system.cpu.l2cache.sampled_refs 99904 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84499 # number of replacements +system.cpu.l2cache.sampled_refs 99950 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16410.322643 # Cycle average of tags in use -system.cpu.l2cache.total_refs 392384 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16402.920353 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423239 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61955 # number of writebacks -system.cpu.numCycles 2205428201 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14473307 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 14 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 33045 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 831088395 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 23088197 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4934346294 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3102230072 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2427283324 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 719527974 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239479384 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32278343 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1182512267 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 368579547 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 22008768 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 170264872 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21765105 # count of temporary serializing insts renamed -system.cpu.timesIdled 5236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.l2cache.writebacks 61948 # number of writebacks +system.cpu.memDep0.conflictingLoads 460341314 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 141106002 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 301399339 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 2205318177 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 17694861 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 27117 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 826425901 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 23298995 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4917191691 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3093611594 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2420068259 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 717791884 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239759977 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32521130 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1175289009 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 369621228 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21984761 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 170791702 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21775082 # count of temporary serializing insts renamed +system.cpu.timesIdled 43184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr deleted file mode 100644 index 320065be7..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index b267c8dc4..8d0eebe28 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=dtb itb tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,9 +26,11 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 -simulate_stalls=false +simulate_data_stalls=false +simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 @@ -50,6 +55,7 @@ cmd=gzip input.log 1 cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 @@ -58,6 +64,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -66,6 +73,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port @@ -73,7 +81,9 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index ce05ca938..d1dad3acf 100644..100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 16 2009 00:17:12 +M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase +M5 started Feb 16 2009 00:46:25 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py long/00.gzip/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Feb 24 2008 13:27:50 -M5 started Mon Feb 25 16:16:45 2008 -M5 executing on tater -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2070157841000 because target called exit() +Exiting @ tick 744764119000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index a5fcdb950..d5f28736a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3930303 # Simulator instruction rate (inst/s) -host_mem_usage 176592 # Number of bytes of host memory used -host_seconds 378.98 # Real time elapsed on the host -host_tick_rate 1965156849 # Simulator tick rate (ticks/s) +host_inst_rate 3714547 # Simulator instruction rate (inst/s) +host_mem_usage 197792 # Number of bytes of host memory used +host_seconds 401.00 # Real time elapsed on the host +host_tick_rate 1857278454 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514761 # Number of instructions simulated -sim_seconds 0.744760 # Number of seconds simulated -sim_ticks 744759833500 # Number of ticks simulated +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 0.744764 # Number of seconds simulated +sim_ticks 744764119000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1489519668 # number of cpu cycles simulated -system.cpu.num_insts 1489514761 # Number of instructions executed -system.cpu.num_refs 569364430 # Number of memory references -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr deleted file mode 100644 index 802ce964e..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7007 -warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 6c34c6dee..90217b2a5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -23,6 +26,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +numThreads=1 phase=0 progress_interval=0 system=system @@ -39,16 +43,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -57,8 +59,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -79,16 +79,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -97,8 +95,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -119,16 +115,14 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -137,8 +131,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -166,6 +158,7 @@ cmd=gzip input.log 1 cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing egid=100 env= +errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 @@ -174,6 +167,7 @@ max_stack_size=67108864 output=cout pid=100 ppid=99 +simpoint=0 system=system uid=100 @@ -190,7 +184,9 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= -latency=1 +latency=30000 +latency_var=0 +null=false range=0:134217727 zero=false port=system.membus.port[0] diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..eabe42249 --- /dev/null +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 5f4ac4eab..d75186ab5 100644..100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Mar 16 2009 00:51:12 +M5 revision 208de84f046d 6013 default tip +M5 started Mar 16 2009 00:51:29 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Duplicating 262144 bytes @@ -29,16 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -Exiting @ tick 744759833500 because target called exit() +Exiting @ tick 2076000877000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 49a7103b2..8851d2d2a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,244 +1,217 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1554729 # Simulator instruction rate (inst/s) -host_mem_usage 223840 # Number of bytes of host memory used -host_seconds 958.05 # Real time elapsed on the host -host_tick_rate 2160793398 # Simulator tick rate (ticks/s) +host_inst_rate 1328193 # Simulator instruction rate (inst/s) +host_mem_usage 205396 # Number of bytes of host memory used +host_seconds 1121.47 # Real time elapsed on the host +host_tick_rate 1851148785 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514761 # Number of instructions simulated -sim_seconds 2.070158 # Number of seconds simulated -sim_ticks 2070157841000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16192.525780 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13192.525780 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3132687000 # number of ReadReq miss cycles +sim_insts 1489523295 # Number of instructions simulated +sim_seconds 2.076001 # Number of seconds simulated +sim_ticks 2076000877000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21085.380854 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.380854 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4079726000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2552292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3499268000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26999.993742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.993742 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166527036 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8629360000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 319606 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7670542000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 319606 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1255.282200 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22924.794034 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 11762047000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21977044000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses -system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10222834000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 20437801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22924.794034 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568845259 # number of overall hits -system.cpu.dcache.overall_miss_latency 11762047000 # number of overall miss cycles +system.cpu.dcache.overall_hits 568846579 # number of overall hits +system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses -system.cpu.dcache.overall_misses 513071 # number of overall misses +system.cpu.dcache.overall_misses 513081 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10222834000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 20437801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 449114 # number of replacements -system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 449125 # number of replacements +system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.499108 # Cycle average of tags in use -system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 373865000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316430 # number of writebacks -system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26988.160291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23988.160291 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1489518537 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 29633000 # number of ReadReq miss cycles +system.cpu.dcache.tagsinuse 4095.229973 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 567696000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316424 # number of writebacks +system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 26339000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1356574.259563 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1489519635 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26988.160291 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency -system.cpu.icache.demand_hits 1489518537 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 29633000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency +system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses +system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 26339000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1489519635 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26988.160291 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1489518537 # number of overall hits -system.cpu.icache.overall_miss_latency 29633000 # number of overall miss cycles +system.cpu.icache.overall_hits 1485111905 # number of overall hits +system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 1098 # number of overall misses +system.cpu.icache.overall_misses 1107 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 26339000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 115 # number of replacements -system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. +system.cpu.icache.replacements 118 # number of replacements +system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.563559 # Cycle average of tags in use -system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 906.413760 # Cycle average of tags in use +system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 259745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5974135000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 259745 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857195000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 259745 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 160837 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 775698000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173342 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33726 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 370986000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173342 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33726 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232066 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1377677000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 160849 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1754688000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.173408 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33744 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1349760000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33744 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59901 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316430 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316430 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.429642 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 160837 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6749833000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.645974 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 293471 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 160849 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15260908000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645963 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 293479 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3228181000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.645974 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 293471 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11739160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645963 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 293479 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 454308 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 160837 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6749833000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.645974 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 293471 # number of overall misses +system.cpu.l2cache.overall_hits 160849 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15260908000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645963 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 293479 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3228181000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.645974 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 293471 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11739160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645963 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 293479 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 82889 # number of replacements -system.cpu.l2cache.sampled_refs 98333 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 82908 # number of replacements +system.cpu.l2cache.sampled_refs 98342 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16360.066474 # Cycle average of tags in use -system.cpu.l2cache.total_refs 337247 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16358.086686 # Cycle average of tags in use +system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61877 # number of writebacks +system.cpu.l2cache.writebacks 61864 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4140315682 # number of cpu cycles simulated -system.cpu.num_insts 1489514761 # Number of instructions executed -system.cpu.num_refs 569364430 # Number of memory references -system.cpu.workload.PROG:num_syscalls 19 # Number of system calls +system.cpu.numCycles 4152001754 # number of cpu cycles simulated +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_refs 569365767 # Number of memory references +system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr deleted file mode 100644 index 2a6ac4135..000000000 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ /dev/null @@ -1,2 +0,0 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 -warn: Entering event queue @ 0. Starting simulation... |