diff options
Diffstat (limited to 'tests/long/00.gzip/ref/sparc')
| -rwxr-xr-x | tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 56 |
2 files changed, 33 insertions, 31 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 0c73642e7..ed5277c40 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2010 02:45:56 -M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip -M5 started May 12 2010 02:48:22 +M5 compiled Jun 6 2010 04:01:36 +M5 revision ba1a0193c050 7448 default tip +M5 started Jun 6 2010 04:02:01 M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 74618889d..57777fec7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 141900 # Simulator instruction rate (inst/s) -host_mem_usage 208776 # Number of bytes of host memory used -host_seconds 9905.67 # Real time elapsed on the host -host_tick_rate 109908342 # Simulator tick rate (ticks/s) +host_inst_rate 109148 # Simulator instruction rate (inst/s) +host_mem_usage 208820 # Number of bytes of host memory used +host_seconds 12878.07 # Real time elapsed on the host +host_tick_rate 84540245 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618369 # Number of instructions simulated sim_seconds 1.088715 # Number of seconds simulated @@ -23,14 +23,14 @@ system.cpu.commit.COM:committed_per_cycle::samples 1942378796 system.cpu.commit.COM:committed_per_cycle::mean 0.766863 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 1.200662 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 1072972593 55.24% 55.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 568760584 29.28% 84.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 118179777 6.08% 90.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 122167717 6.29% 96.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 27965504 1.44% 98.34% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 8603273 0.44% 98.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 11084471 0.57% 99.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 4630000 0.24% 99.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 1072972593 55.24% 55.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 568760584 29.28% 84.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 118179777 6.08% 90.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 122167717 6.29% 96.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 27965504 1.44% 98.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 8603273 0.44% 98.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 11084471 0.57% 99.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 4630000 0.24% 99.59% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 8014877 0.41% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -146,14 +146,14 @@ system.cpu.fetch.rateDist::samples 2175919229 # Nu system.cpu.fetch.rateDist::mean 1.693886 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.844671 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 290862633 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) @@ -295,14 +295,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::samples 2175919229 system.cpu.iq.ISSUE:issued_per_cycle::mean 0.909807 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.157368 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 1068255963 49.09% 49.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 579314637 26.62% 75.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 292421261 13.44% 89.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 161809686 7.44% 96.59% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 50369072 2.31% 98.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14937591 0.69% 99.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 7897011 0.36% 99.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 777368 0.04% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 1068255963 49.09% 49.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 579314637 26.62% 75.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 292421261 13.44% 89.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 161809686 7.44% 96.59% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 50369072 2.31% 98.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 14937591 0.69% 99.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 7897011 0.36% 99.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 777368 0.04% 99.99% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 136640 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle |