diff options
Diffstat (limited to 'tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt | 114 |
1 files changed, 57 insertions, 57 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 2cd851868..fd5733aad 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1747793 # Simulator instruction rate (inst/s) -host_mem_usage 207260 # Number of bytes of host memory used -host_seconds 926.52 # Real time elapsed on the host -host_tick_rate 1958830620 # Simulator tick rate (ticks/s) +host_inst_rate 995738 # Simulator instruction rate (inst/s) +host_mem_usage 205000 # Number of bytes of host memory used +host_seconds 1626.30 # Real time elapsed on the host +host_tick_rate 1115968300 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619365942 # Number of instructions simulated +sim_insts 1619365954 # Number of instructions simulated sim_seconds 1.814897 # Number of seconds simulated -sim_ticks 1814896671000 # Number of ticks simulated +sim_ticks 1814896735000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 419042118 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 20939.027041 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17939.027041 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 440755 # number of replacements system.cpu.dcache.sampled_refs 444851 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.900352 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.900211 # Cycle average of tags in use system.cpu.dcache.total_refs 606783323 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 779366000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 779430000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 308934 # number of writebacks -system.cpu.icache.ReadReq_accesses 1186516694 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1186516703 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1186515973 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_hits 1186515981 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1645653.221914 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1643373.934903 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1186516694 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1186516703 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1186515973 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_hits 1186515981 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.demand_misses 721 # number of demand (read+write) misses +system.cpu.icache.demand_misses 722 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1186516694 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1186516703 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1186515973 # number of overall hits -system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles +system.cpu.icache.overall_hits 1186515981 # number of overall hits +system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.overall_misses 721 # number of overall misses +system.cpu.icache.overall_misses 722 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 659.162719 # Cycle average of tags in use -system.cpu.icache.total_refs 1186515973 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 660.162690 # Cycle average of tags in use +system.cpu.icache.total_refs 1186515981 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -134,16 +134,16 @@ system.cpu.l2cache.ReadExReq_misses 247042 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 9881680000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 247042 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 198530 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 198531 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 165128 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1736904000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.168247 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33402 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1336080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.168247 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33402 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 1736956000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.168251 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33403 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1336120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.168251 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33403 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 65104 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency @@ -157,50 +157,50 @@ system.cpu.l2cache.Writeback_accesses 308934 # nu system.cpu.l2cache.Writeback_hits 308934 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.437930 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.437895 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 445572 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 445573 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 165128 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14583088000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.629402 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 280444 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14583140000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.629403 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 280445 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11217760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.629402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 280444 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11217800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.629403 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 280445 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 445572 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 445573 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 165128 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14583088000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.629402 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 280444 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14583140000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.629403 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 280445 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11217760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.629402 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 280444 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11217800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.629403 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 280445 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 82238 # number of replacements -system.cpu.l2cache.sampled_refs 97728 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 82239 # number of replacements +system.cpu.l2cache.sampled_refs 97729 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16489.299090 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16489.401861 # Cycle average of tags in use system.cpu.l2cache.total_refs 335982 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61724 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3629793342 # number of cpu cycles simulated -system.cpu.num_insts 1619365942 # Number of instructions executed +system.cpu.numCycles 3629793470 # number of cpu cycles simulated +system.cpu.num_insts 1619365954 # Number of instructions executed system.cpu.num_refs 607228174 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls |