diff options
Diffstat (limited to 'tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 60806dc72..59d079222 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1181561 # Simulator instruction rate (inst/s) -host_mem_usage 194380 # Number of bytes of host memory used -host_seconds 1370.53 # Real time elapsed on the host -host_tick_rate 1324103876 # Simulator tick rate (ticks/s) +host_inst_rate 992380 # Simulator instruction rate (inst/s) +host_mem_usage 196544 # Number of bytes of host memory used +host_seconds 1631.80 # Real time elapsed on the host +host_tick_rate 1112100106 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619366736 # Number of instructions simulated sim_seconds 1.814727 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 506760 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.901154 # Average occupied blocks per context system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42325.964954 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39325.964954 # average overall mshr miss latency @@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.322346 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 660.164909 # Average occupied blocks per context system.cpu.icache.overall_accesses 1186516703 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses 277801 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.052737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.452189 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1728.087970 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14817.313734 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 442788 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |