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-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt18
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 120240c59..1cc5290ea 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1667736 # Simulator instruction rate (inst/s)
-host_mem_usage 231728 # Number of bytes of host memory used
-host_seconds 972.27 # Real time elapsed on the host
-host_tick_rate 1854683738 # Simulator tick rate (ticks/s)
+host_inst_rate 2023797 # Simulator instruction rate (inst/s)
+host_mem_usage 210248 # Number of bytes of host memory used
+host_seconds 801.21 # Real time elapsed on the host
+host_tick_rate 2250658484 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493983 # Number of instructions simulated
sim_seconds 1.803259 # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu.dcache.demand_mshr_misses 442048 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999731 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.322357 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
@@ -173,10 +173,10 @@ system.cpu.l2cache.demand_mshr_misses 89468 # nu
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.057043 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.494010 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
@@ -218,6 +218,6 @@ system.cpu.num_int_register_writes 1617994650 # nu
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_mem_refs 607228182 # number of memory refs
system.cpu.num_store_insts 188186057 # Number of store instructions
-system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
+system.cpu.workload.num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------