diff options
Diffstat (limited to 'tests/long/00.gzip/ref')
12 files changed, 1495 insertions, 1505 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index cdf647d08..b11fadb7f 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 81484db61..9acd0ed7e 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 14:50:17 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 16:10:09 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -41,4 +41,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 145301847500 because target called exit() +Exiting @ tick 144450185500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 5c2b0fbb8..bcb696265 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.145302 # Number of seconds simulated -sim_ticks 145301847500 # Number of ticks simulated +sim_seconds 0.144450 # Number of seconds simulated +sim_ticks 144450185500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168398 # Simulator instruction rate (inst/s) -host_tick_rate 43264868 # Simulator tick rate (ticks/s) -host_mem_usage 252140 # Number of bytes of host memory used -host_seconds 3358.43 # Real time elapsed on the host +host_inst_rate 180758 # Simulator instruction rate (inst/s) +host_tick_rate 46168195 # Simulator tick rate (ticks/s) +host_mem_usage 205240 # Number of bytes of host memory used +host_seconds 3128.78 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125931819 # DTB read hits -system.cpu.dtb.read_misses 26714 # DTB read misses +system.cpu.dtb.read_hits 125584378 # DTB read hits +system.cpu.dtb.read_misses 26780 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125958533 # DTB read accesses -system.cpu.dtb.write_hits 41424543 # DTB write hits -system.cpu.dtb.write_misses 32276 # DTB write misses +system.cpu.dtb.read_accesses 125611158 # DTB read accesses +system.cpu.dtb.write_hits 41433696 # DTB write hits +system.cpu.dtb.write_misses 32002 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 41456819 # DTB write accesses -system.cpu.dtb.data_hits 167356362 # DTB hits -system.cpu.dtb.data_misses 58990 # DTB misses +system.cpu.dtb.write_accesses 41465698 # DTB write accesses +system.cpu.dtb.data_hits 167018074 # DTB hits +system.cpu.dtb.data_misses 58782 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 167415352 # DTB accesses -system.cpu.itb.fetch_hits 71387266 # ITB hits +system.cpu.dtb.data_accesses 167076856 # DTB accesses +system.cpu.itb.fetch_hits 70952399 # ITB hits system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 71387306 # ITB accesses +system.cpu.itb.fetch_accesses 70952439 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 290603696 # number of cpu cycles simulated +system.cpu.numCycles 288900372 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 81919814 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 75390266 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4129357 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77614173 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69618230 # Number of BTB hits +system.cpu.BPredUnit.lookups 81329377 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74804974 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4133006 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77032590 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69317648 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1955958 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 74192269 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 739424750 # Number of instructions fetch has processed -system.cpu.fetch.Branches 81919814 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71574188 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 139080989 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17172234 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 64410456 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1953991 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 213 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 73654881 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 736311086 # Number of instructions fetch has processed +system.cpu.fetch.Branches 81329377 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71271639 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 138478958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 16551941 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 64286783 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 71387266 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1210642 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 290534603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.545049 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.198246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 70952399 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1183706 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 288831482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.549276 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.199825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151453614 52.13% 52.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11687885 4.02% 56.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15898742 5.47% 61.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15854935 5.46% 67.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13240035 4.56% 71.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15603650 5.37% 77.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6697784 2.31% 79.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3574182 1.23% 80.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56523776 19.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 150352524 52.06% 52.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11670569 4.04% 56.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15804098 5.47% 61.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15798949 5.47% 67.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13114109 4.54% 71.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15608541 5.40% 76.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6620136 2.29% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3484931 1.21% 80.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56377625 19.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 290534603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281895 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.544444 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 90310656 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 50731551 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 126219695 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10423604 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12849097 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4446391 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 727740839 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3152 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12849097 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 98621596 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12675857 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 639 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 123066068 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43321346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 713725381 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 266 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 34127954 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3740820 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 543893835 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 937350842 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 937348775 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2067 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 288831482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.281514 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.548668 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 89767727 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 50572891 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 125759213 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10322601 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12409050 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4445174 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 884 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 724769065 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3300 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12409050 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 98007088 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12678191 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 619 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 122576240 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43160294 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 711155131 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 33840558 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3866582 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 542435988 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 934956599 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 934954553 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2046 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 80038946 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 85210895 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 131427932 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43788464 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14719547 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6869694 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 643138163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 78581099 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 84659517 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 130961315 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43800509 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14632120 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10811841 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 641773186 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 621184561 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 428348 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 76303449 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41228761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 620620587 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 312645 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 75146534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 39896926 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 290534603 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.138074 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876724 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 288831482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.148729 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.863512 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 70371393 24.22% 24.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 59001774 20.31% 44.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 56407615 19.42% 63.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31734464 10.92% 74.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 32252552 11.10% 85.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24569230 8.46% 94.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11680867 4.02% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3911059 1.35% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 605649 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69246295 23.97% 23.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 56834943 19.68% 43.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 56336980 19.51% 63.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34937865 12.10% 75.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31450731 10.89% 86.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24967668 8.64% 94.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10438059 3.61% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3923057 1.36% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 695884 0.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 290534603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 288831482 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4149748 79.41% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 46 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 644138 12.33% 91.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 431804 8.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3711133 78.36% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 47 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 592679 12.51% 90.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 432117 9.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 450716451 72.56% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7786 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 128329931 20.66% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 42130345 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 450541493 72.60% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7929 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 127924018 20.61% 93.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 42147099 6.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 621184561 # Type of FU issued -system.cpu.iq.rate 2.137566 # Inst issue rate -system.cpu.iq.fu_busy_cnt 5225736 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008413 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1538554428 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 719791910 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 609163875 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3381 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1868 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1606 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 626408589 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1708 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11777609 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 620620587 # Type of FU issued +system.cpu.iq.rate 2.148217 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4735976 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007631 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1535117897 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 716922572 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 608986825 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3380 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1870 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 625354857 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1706 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11780563 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16913890 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 148570 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 370604 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4337143 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16447273 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 150139 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4778 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4349188 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5917 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 50743 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5903 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 50771 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12849097 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1534890 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101054 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 688747962 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2386448 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 131427932 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43788464 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 12409050 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1537752 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 101062 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 686807741 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2379158 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 130961315 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43800509 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 40995 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13802 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 370604 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4041048 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 603771 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4644819 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 613556554 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 125958678 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7628007 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 40948 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13806 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4778 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4044271 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 603642 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4647913 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 613128186 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 125611295 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7492401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 45609769 # number of nop insts executed -system.cpu.iew.exec_refs 167435052 # number of memory reference insts executed -system.cpu.iew.exec_branches 68567792 # Number of branches executed -system.cpu.iew.exec_stores 41476374 # Number of stores executed -system.cpu.iew.exec_rate 2.111317 # Inst execution rate -system.cpu.iew.wb_sent 610651273 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 609165481 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420066604 # num instructions producing a value -system.cpu.iew.wb_consumers 531633628 # num instructions consuming a value +system.cpu.iew.exec_nop 45034525 # number of nop insts executed +system.cpu.iew.exec_refs 167096489 # number of memory reference insts executed +system.cpu.iew.exec_branches 68658345 # Number of branches executed +system.cpu.iew.exec_stores 41485194 # Number of stores executed +system.cpu.iew.exec_rate 2.122282 # Inst execution rate +system.cpu.iew.wb_sent 610318268 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 608988422 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420036286 # num instructions producing a value +system.cpu.iew.wb_consumers 531421352 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.096207 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790143 # average fanout of values written-back +system.cpu.iew.wb_rate 2.107953 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 86736991 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4128553 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 277685506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.167405 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.598933 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 276422432 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.177309 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.603924 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91049633 32.79% 32.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 76164348 27.43% 60.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 31609265 11.38% 71.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9610599 3.46% 75.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10212120 3.68% 78.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21618987 7.79% 86.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6091791 2.19% 88.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2481977 0.89% 89.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 28846786 10.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 90291943 32.66% 32.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 75645741 27.37% 60.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 32420379 11.73% 71.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8741969 3.16% 74.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10320203 3.73% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19633028 7.10% 85.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6964693 2.52% 88.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5325361 1.93% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 27079115 9.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 277685506 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle system.cpu.commit.count 601856963 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 28846786 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 27079115 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 937368285 # The number of ROB reads -system.cpu.rob.rob_writes 1390043178 # The number of ROB writes -system.cpu.timesIdled 2213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 69093 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 935932678 # The number of ROB reads +system.cpu.rob.rob_writes 1385724156 # The number of ROB writes +system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.513840 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.513840 # CPI: Total CPI of All Threads -system.cpu.ipc 1.946130 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.946130 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 864034550 # number of integer regfile reads -system.cpu.int_regfile_writes 501250515 # number of integer regfile writes -system.cpu.fp_regfile_reads 281 # number of floating regfile reads +system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads +system.cpu.ipc 1.957604 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.957604 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 863490102 # number of integer regfile reads +system.cpu.int_regfile_writes 500818441 # number of integer regfile writes +system.cpu.fp_regfile_reads 272 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.tagsinuse 800.952347 # Cycle average of tags in use -system.cpu.icache.total_refs 71385990 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 943 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 75700.943796 # Average number of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.tagsinuse 801.236568 # Cycle average of tags in use +system.cpu.icache.total_refs 70951127 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 75160.092161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 800.952347 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.391090 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 71385990 # number of ReadReq hits -system.cpu.icache.demand_hits 71385990 # number of demand (read+write) hits -system.cpu.icache.overall_hits 71385990 # number of overall hits -system.cpu.icache.ReadReq_misses 1276 # number of ReadReq misses -system.cpu.icache.demand_misses 1276 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1276 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 46038500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 46038500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 46038500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 71387266 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 71387266 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 71387266 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 801.236568 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.391229 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 70951127 # number of ReadReq hits +system.cpu.icache.demand_hits 70951127 # number of demand (read+write) hits +system.cpu.icache.overall_hits 70951127 # number of overall hits +system.cpu.icache.ReadReq_misses 1272 # number of ReadReq misses +system.cpu.icache.demand_misses 1272 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1272 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 45919500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 45919500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 45919500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 70952399 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 70952399 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 70952399 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36080.329154 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36080.329154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36080.329154 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36100.235849 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36100.235849 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36100.235849 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 333 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 333 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 943 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 943 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 943 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 944 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 944 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 944 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33661000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33661000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33661000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33676000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33676000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33676000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35695.652174 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35695.652174 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35695.652174 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35673.728814 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 470870 # number of replacements -system.cpu.dcache.tagsinuse 4093.952106 # Cycle average of tags in use -system.cpu.dcache.total_refs 151563529 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 474966 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 319.103955 # Average number of references to valid blocks. +system.cpu.dcache.replacements 470690 # number of replacements +system.cpu.dcache.tagsinuse 4093.940031 # Cycle average of tags in use +system.cpu.dcache.total_refs 151212527 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 474786 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 318.485648 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4093.952106 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 113415940 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38147585 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 151563525 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 151563525 # number of overall hits -system.cpu.dcache.ReadReq_misses 731363 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1303736 # number of WriteReq misses -system.cpu.dcache.demand_misses 2035099 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2035099 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11802867000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 19634898764 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 31437765764 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 31437765764 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114147303 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4093.940031 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 113064898 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38147626 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 151212524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 151212524 # number of overall hits +system.cpu.dcache.ReadReq_misses 732041 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1303695 # number of WriteReq misses +system.cpu.dcache.demand_misses 2035736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2035736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11783533000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 19632740219 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 31416273219 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 31416273219 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 113796939 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153598624 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153598624 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006407 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.033047 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013249 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013249 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16138.178989 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15060.486758 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15447.782031 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15447.782031 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 886996 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 153248260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 153248260 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.006433 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.033046 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.013284 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013284 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16096.821080 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15059.304683 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15432.390653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15432.390653 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 804496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7646.517241 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6935.310345 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423193 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 512453 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1047680 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1560133 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1560133 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218910 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256056 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 474966 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 474966 # number of overall MSHR misses +system.cpu.dcache.writebacks 423044 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 513277 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1047673 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1560950 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1560950 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 218764 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 256022 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 474786 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 474786 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1640097000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3028332494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4668429494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4668429494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1640072500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3027658494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4667730994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4667730994 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001918 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001922 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003092 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7492.106345 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11826.836684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9828.976167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9828.976167 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.003098 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003098 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.994478 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.774715 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74473 # number of replacements -system.cpu.l2cache.tagsinuse 17668.898791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 478122 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90370 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.290716 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74463 # number of replacements +system.cpu.l2cache.tagsinuse 17661.712037 # Cycle average of tags in use +system.cpu.l2cache.total_refs 478021 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90363 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.290008 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1750.296576 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15918.602215 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053415 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485797 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186900 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423193 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 196240 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 383140 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 383140 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32953 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59816 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92769 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92769 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1133504500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2066596000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3200100500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3200100500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219853 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423193 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256056 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 475909 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 475909 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.149887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.233605 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194930 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194930 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34397.611750 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.217601 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34495.364831 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34495.364831 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 453500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1743.919943 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15917.792095 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053220 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485772 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 186750 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 423044 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 196218 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 382968 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 382968 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32958 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92762 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92762 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1133680000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2065878500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3199558500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3199558500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 219708 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 423044 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 256022 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 475730 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 475730 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.150008 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.233589 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.194989 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.194989 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34397.718308 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34544.152565 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34492.125008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34492.125008 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 76 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5967.105263 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59331 # number of writebacks +system.cpu.l2cache.writebacks 59330 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32953 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59816 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92769 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92769 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32958 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92762 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1022169500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1878238500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2900408000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2900408000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1022345000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877543500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2899888500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2899888500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149887 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233605 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194930 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194930 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.011926 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31400.269159 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.840626 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.840626 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150008 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.194989 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.194989 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.631046 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31394.948498 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index fea8ea4a1..e2efd077d 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index a9117199d..ffc55a28a 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:27:45 -gem5 started Aug 17 2011 20:12:24 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 12:27:58 +gem5 started Aug 20 2011 12:28:18 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 181028108500 because target called exit() +Exiting @ tick 177134936000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 701011da6..be7b06491 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.181028 # Number of seconds simulated -sim_ticks 181028108500 # Number of ticks simulated +sim_seconds 0.177135 # Number of seconds simulated +sim_ticks 177134936000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110603 # Simulator instruction rate (inst/s) -host_tick_rate 33239774 # Simulator tick rate (ticks/s) -host_mem_usage 263548 # Number of bytes of host memory used -host_seconds 5446.13 # Real time elapsed on the host -sim_insts 602359805 # Number of instructions simulated +host_inst_rate 142557 # Simulator instruction rate (inst/s) +host_tick_rate 41921641 # Simulator tick rate (ticks/s) +host_mem_usage 216920 # Number of bytes of host memory used +host_seconds 4225.38 # Real time elapsed on the host +sim_insts 602359810 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 362056218 # number of cpu cycles simulated +system.cpu.numCycles 354269873 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 93448154 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 85911629 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3923569 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 88397798 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81789381 # Number of BTB hits +system.cpu.BPredUnit.lookups 91159436 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 84245505 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4004866 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 86334569 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 80046410 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1790445 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1821 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 79878814 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 718366767 # Number of instructions fetch has processed -system.cpu.fetch.Branches 93448154 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83579826 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162526152 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20714981 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 102669649 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 77174070 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1530906 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 361172763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.127936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.978152 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1704802 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1819 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 76808344 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 703901675 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91159436 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81751212 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 159188980 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 18469359 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 103024732 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 658 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 74435954 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1343690 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 353410599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.128136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.980644 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198646777 55.00% 55.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25571456 7.08% 62.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 19827264 5.49% 67.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 25093348 6.95% 74.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12488036 3.46% 77.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13650153 3.78% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4767489 1.32% 83.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7787203 2.16% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53341037 14.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 194221784 54.96% 54.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25626631 7.25% 62.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 19263980 5.45% 67.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24389254 6.90% 74.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11789340 3.34% 77.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13441910 3.80% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4603453 1.30% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7798173 2.21% 85.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52276074 14.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 361172763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258104 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.984130 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 102343616 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83020024 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 140521738 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19192459 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16094926 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6886310 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2563 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 756045465 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7091 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 16094926 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 115645953 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9675212 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 105916 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 146342748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73308008 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 741744489 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59347402 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10155907 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 308 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 765934734 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3449682594 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3449682466 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 353410599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257316 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.986908 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 98916904 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83485006 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 137131028 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19492362 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14385299 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6301332 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 2598 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 740264204 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 7138 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14385299 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 111881934 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9577242 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 106466 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 143552765 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73906893 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 727334722 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 296 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59781135 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10308783 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 341 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 753003460 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3381092272 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3381092144 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 138517335 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6417 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6420 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 130475053 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 183427028 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85118109 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 19617047 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24959505 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 714042486 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7344 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 668482439 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 813187 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 110903932 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 272103092 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1046 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 361172763 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.850866 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.720469 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 125586053 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6434 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6436 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 132024310 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 179771780 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 82868403 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 19149565 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24496609 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 702530034 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7346 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 663102893 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 740706 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 99626728 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 237214631 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1047 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 353410599 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.876296 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734600 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89609578 24.81% 24.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 92103808 25.50% 50.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76957239 21.31% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 43677932 12.09% 83.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 26190048 7.25% 90.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 17902760 4.96% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7158113 1.98% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6378593 1.77% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1194692 0.33% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 85472706 24.19% 24.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 90623075 25.64% 49.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75986397 21.50% 71.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 42524156 12.03% 83.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 25503318 7.22% 90.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 18123112 5.13% 95.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7244001 2.05% 97.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6628954 1.88% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1304880 0.37% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 361172763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 353410599 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 174743 4.36% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2924154 73.03% 77.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 905037 22.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202122 4.87% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2984901 71.87% 76.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 966402 23.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 414572332 62.02% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6557 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 174888345 26.16% 88.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79015202 11.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412611240 62.22% 62.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6564 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 172508534 26.02% 88.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 77976552 11.76% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 668482439 # Type of FU issued -system.cpu.iq.rate 1.846350 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4003934 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005990 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1702954726 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 825626408 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 654174988 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 663102893 # Type of FU issued +system.cpu.iq.rate 1.871745 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4153425 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006264 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1684510480 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 802175669 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 650244511 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 672486353 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 667256298 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 28890587 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 29664426 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34474432 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123741 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 677004 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 14897095 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30819183 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 223952 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11801 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12647388 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 16171 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12604 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 13674 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12619 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16094926 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 778321 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 50892 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 714119394 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2033981 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 183427028 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85118109 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6015 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12993 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 677004 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4081658 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 498372 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4580030 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 660769173 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 171345747 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7713266 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 14385299 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 811787 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 58163 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 702606824 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1856146 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 179771780 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 82868403 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6016 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13064 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5095 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11801 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4163103 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495424 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4658527 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 656117429 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169139334 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6985464 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69564 # number of nop insts executed -system.cpu.iew.exec_refs 248875630 # number of memory reference insts executed -system.cpu.iew.exec_branches 76892303 # Number of branches executed -system.cpu.iew.exec_stores 77529883 # Number of stores executed -system.cpu.iew.exec_rate 1.825046 # Inst execution rate -system.cpu.iew.wb_sent 656292597 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 654175004 # cumulative count of insts written-back -system.cpu.iew.wb_producers 424501609 # num instructions producing a value -system.cpu.iew.wb_consumers 659455960 # num instructions consuming a value +system.cpu.iew.exec_nop 69444 # number of nop insts executed +system.cpu.iew.exec_refs 245837823 # number of memory reference insts executed +system.cpu.iew.exec_branches 76466943 # Number of branches executed +system.cpu.iew.exec_stores 76698489 # Number of stores executed +system.cpu.iew.exec_rate 1.852027 # Inst execution rate +system.cpu.iew.wb_sent 652257551 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 650244527 # cumulative count of insts written-back +system.cpu.iew.wb_producers 423314128 # num instructions producing a value +system.cpu.iew.wb_consumers 657393243 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.806833 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.643715 # average fanout of values written-back +system.cpu.iew.wb_rate 1.835450 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.643928 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 111769419 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6298 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3982936 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 345077838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.745577 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.124891 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 100255909 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6299 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4064207 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 339025301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.776740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.152545 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 111837000 32.41% 32.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 108539519 31.45% 63.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49573446 14.37% 78.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10197254 2.96% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23493632 6.81% 87.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14599312 4.23% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8154465 2.36% 94.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1281875 0.37% 94.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 17401335 5.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 108189269 31.91% 31.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 106528342 31.42% 63.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49314404 14.55% 77.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9858111 2.91% 80.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23334525 6.88% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14310366 4.22% 91.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7925881 2.34% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1332062 0.39% 94.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18232341 5.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 345077838 # Number of insts commited each cycle -system.cpu.commit.count 602359856 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 339025301 # Number of insts commited each cycle +system.cpu.commit.count 602359861 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173609 # Number of memory references committed -system.cpu.commit.loads 148952595 # Number of loads committed +system.cpu.commit.refs 219173611 # Number of memory references committed +system.cpu.commit.loads 148952596 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828602 # Number of branches committed +system.cpu.commit.branches 70828603 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522643 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522647 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 17401335 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 18232341 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1041805166 # The number of ROB reads -system.cpu.rob.rob_writes 1444392656 # The number of ROB writes -system.cpu.timesIdled 37065 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 883455 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359805 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated -system.cpu.cpi 0.601063 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.601063 # CPI: Total CPI of All Threads -system.cpu.ipc 1.663719 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.663719 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3299876653 # number of integer regfile reads -system.cpu.int_regfile_writes 679084326 # number of integer regfile writes +system.cpu.rob.rob_reads 1023408118 # The number of ROB reads +system.cpu.rob.rob_writes 1419658807 # The number of ROB writes +system.cpu.timesIdled 37049 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 859274 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359810 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated +system.cpu.cpi 0.588137 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.588137 # CPI: Total CPI of All Threads +system.cpu.ipc 1.700285 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.700285 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3276148182 # number of integer regfile reads +system.cpu.int_regfile_writes 676030301 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 960654614 # number of misc regfile reads -system.cpu.misc_regfile_writes 2658 # number of misc regfile writes -system.cpu.icache.replacements 39 # number of replacements -system.cpu.icache.tagsinuse 659.213464 # Cycle average of tags in use -system.cpu.icache.total_refs 77173072 # Total number of references to valid blocks. +system.cpu.misc_regfile_reads 943785902 # number of misc regfile reads +system.cpu.misc_regfile_writes 2660 # number of misc regfile writes +system.cpu.icache.replacements 38 # number of replacements +system.cpu.icache.tagsinuse 657.730766 # Cycle average of tags in use +system.cpu.icache.total_refs 74434959 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 761 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 101410.081472 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 97812.035480 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 659.213464 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.321882 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 77173072 # number of ReadReq hits -system.cpu.icache.demand_hits 77173072 # number of demand (read+write) hits -system.cpu.icache.overall_hits 77173072 # number of overall hits -system.cpu.icache.ReadReq_misses 998 # number of ReadReq misses -system.cpu.icache.demand_misses 998 # number of demand (read+write) misses -system.cpu.icache.overall_misses 998 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34962500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34962500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34962500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 77174070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 77174070 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 77174070 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 657.730766 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.321158 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 74434959 # number of ReadReq hits +system.cpu.icache.demand_hits 74434959 # number of demand (read+write) hits +system.cpu.icache.overall_hits 74434959 # number of overall hits +system.cpu.icache.ReadReq_misses 995 # number of ReadReq misses +system.cpu.icache.demand_misses 995 # number of demand (read+write) misses +system.cpu.icache.overall_misses 995 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 34724500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 34724500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 34724500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 74435954 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 74435954 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 74435954 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35032.565130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35032.565130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35032.565130 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34898.994975 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34898.994975 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34898.994975 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 762 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 762 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 762 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 234 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 234 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 234 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 761 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 761 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 26035000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 26035000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 26035000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25975000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34166.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34132.720105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 441073 # number of replacements -system.cpu.dcache.tagsinuse 4094.780664 # Cycle average of tags in use -system.cpu.dcache.total_refs 208769486 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445169 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 468.966810 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 87843000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.780664 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999702 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 140903051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 67863771 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1333 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 208766822 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 208766822 # number of overall hits -system.cpu.dcache.ReadReq_misses 249137 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1553760 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1802897 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1802897 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3284237500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 27026235527 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 199500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 30310473027 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30310473027 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 141152188 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 441231 # number of replacements +system.cpu.dcache.tagsinuse 4094.754255 # Cycle average of tags in use +system.cpu.dcache.total_refs 205797010 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 445327 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 462.125607 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87838000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.754255 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999696 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 137942409 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67851936 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1336 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 205794345 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 205794345 # number of overall hits +system.cpu.dcache.ReadReq_misses 249307 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1565595 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1814902 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1814902 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3284045500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 27041000027 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 163000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 30325045527 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 30325045527 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 138191716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1342 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 210569719 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 210569719 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001765 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.022383 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.006706 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.008562 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008562 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13182.455838 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17394.086298 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 22166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 16812.093551 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 16812.093551 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 207609247 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 207609247 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.022553 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.005952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008742 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008742 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13172.696715 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17272.027585 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 20375 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 16708.916254 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 16708.916254 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked @@ -422,72 +422,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 395116 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51340 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1306387 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1357727 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1357727 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197797 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247373 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 445170 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 445170 # number of overall MSHR misses +system.cpu.dcache.writebacks 395260 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51378 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1318197 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1369575 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1369575 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197929 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247398 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 445327 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 445327 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1624472000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2544428527 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4168900527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4168900527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1625138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2544850527 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4169988527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4169988527 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8212.824259 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.797266 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8210.711922 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10286.463621 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72968 # number of replacements -system.cpu.l2cache.tagsinuse 17823.256167 # Cycle average of tags in use -system.cpu.l2cache.total_refs 421257 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.760396 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72978 # number of replacements +system.cpu.l2cache.tagsinuse 17806.299437 # Cycle average of tags in use +system.cpu.l2cache.total_refs 422221 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88511 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.770266 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1903.843188 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15919.412978 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058101 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485822 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165755 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 395116 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 189016 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 354771 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 354771 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32799 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58360 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91159 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91159 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1126738500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2004231000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3130969500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3130969500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198554 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 395116 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247376 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 445930 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 445930 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165189 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235916 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204424 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204424 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34352.830879 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34342.546265 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34346.246668 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34346.246668 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1880.880475 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15925.418963 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057400 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486005 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165873 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 395260 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 189038 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 354911 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 354911 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32814 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91177 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1126440500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2003739500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3130180000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3130180000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198687 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 395260 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247401 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 446088 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 446088 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165154 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235904 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204392 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204392 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34328.045956 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34332.359543 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34330.807111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34330.807111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -496,28 +494,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58122 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32790 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58360 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91150 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91150 # number of overall MSHR misses +system.cpu.l2cache.writebacks 58123 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32806 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91169 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1020255000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822537500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2842792500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2842792500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1019567500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822366000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2841933500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2841933500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165144 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235916 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204404 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204404 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.821592 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31229.223783 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165114 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235904 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204374 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204374 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31078.689874 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31224.680020 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 69d6d5791..80ace0dc5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index f40ea4f95..cea2acb5a 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 16:58:37 -gem5 started Aug 17 2011 16:59:36 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 13:07:22 +gem5 started Aug 20 2011 13:07:33 +gem5 executing on zizzer command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 424846003000 because target called exit() +Exiting @ tick 408816360000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 386994981..58e0bfc8f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,148 +1,148 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.424846 # Number of seconds simulated -sim_ticks 424846003000 # Number of ticks simulated +sim_seconds 0.408816 # Number of seconds simulated +sim_ticks 408816360000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130905 # Simulator instruction rate (inst/s) -host_tick_rate 39566335 # Simulator tick rate (ticks/s) -host_mem_usage 260032 # Number of bytes of host memory used -host_seconds 10737.56 # Real time elapsed on the host +host_inst_rate 166907 # Simulator instruction rate (inst/s) +host_tick_rate 48544601 # Simulator tick rate (ticks/s) +host_mem_usage 212296 # Number of bytes of host memory used +host_seconds 8421.46 # Real time elapsed on the host sim_insts 1405604152 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 849692007 # number of cpu cycles simulated +system.cpu.numCycles 817632721 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103951242 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 92817618 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5441892 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 101027131 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 99845588 # Number of BTB hits +system.cpu.BPredUnit.lookups 103174324 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 92051331 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 5438120 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 100325127 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 99277633 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1240 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 176461208 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1731297968 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103951242 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99846828 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 372380430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 32542357 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 273950532 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1598 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 171982366 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1072419 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 849334249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.043796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.987927 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1230 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 220 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 175005792 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1720391035 # Number of instructions fetch has processed +system.cpu.fetch.Branches 103174324 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99278863 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 370286255 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31094297 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 246539947 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1680 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 170773896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 991956 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 817274934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.110623 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.012258 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 476953819 56.16% 56.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82874443 9.76% 65.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45104012 5.31% 71.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23823207 2.80% 74.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 33449263 3.94% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 34018296 4.01% 81.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14934889 1.76% 83.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7594649 0.89% 84.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 130581671 15.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 446988679 54.69% 54.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 82419688 10.08% 64.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45028734 5.51% 70.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23714407 2.90% 73.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 33177153 4.06% 77.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 33877408 4.15% 81.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14961867 1.83% 83.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7384305 0.90% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 129722693 15.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 849334249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122340 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.037559 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 228750775 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 225010682 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 340329593 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 28702732 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 26540467 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1719853048 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 26540467 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 263479088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 41404306 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55665718 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 333164025 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 129080645 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1702621917 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 27946870 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 65424391 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16478266 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1420563184 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2876973295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2842990293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33983002 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 817274934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126187 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.104112 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 224321388 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 200349407 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 337624010 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 29538890 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 25441239 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1710162106 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 25441239 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 255728945 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34334751 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55175561 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 334633255 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 111961183 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1694040603 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 27905496 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 64677715 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3154928 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1413596061 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2861791975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2827818793 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33973182 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 175792732 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3237844 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3287220 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 297721307 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 456905033 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 186186881 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 277685429 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 94682535 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1573041480 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3078086 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1493571680 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 168879 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 169173312 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193746620 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 834415 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 849334249 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.758520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.350284 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 168825609 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3228150 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3270628 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 258968806 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 454536844 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 185491805 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 260927641 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 90896258 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1566773345 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3062819 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1493172729 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 111198 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 163655037 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 180232812 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 819148 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 817274934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.827014 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.412188 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 177901650 20.95% 20.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 206358445 24.30% 45.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 226462970 26.66% 71.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151667203 17.86% 89.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 64968416 7.65% 97.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14273144 1.68% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6071046 0.71% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1430974 0.17% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 200401 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168134039 20.57% 20.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 190992211 23.37% 43.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210117454 25.71% 69.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 154482053 18.90% 88.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 65263213 7.99% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16377311 2.00% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7979086 0.98% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3751008 0.46% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 178559 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 849334249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 817274934 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 106837 5.02% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 176348 8.29% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1497549 70.41% 83.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 346224 16.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 154618 7.33% 7.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 176227 8.36% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1421289 67.40% 83.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 356622 16.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 886788388 59.37% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2623578 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 886609078 59.38% 59.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2623677 0.18% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued @@ -168,85 +168,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 430759220 28.84% 88.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173400494 11.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 430399729 28.82% 88.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173540245 11.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1493571680 # Type of FU issued -system.cpu.iq.rate 1.757780 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2126958 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3820899737 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1736825318 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1473365597 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17873709 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9212850 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8524107 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1486479437 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9219201 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209970408 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1493172729 # Type of FU issued +system.cpu.iq.rate 1.826214 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2108756 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001412 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3787980335 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1724526520 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1473498966 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17860011 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9206634 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8523998 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1486074999 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9206486 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 205830187 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 54392189 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 142413 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 763229 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 19338739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 52024000 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213849 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 253991 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 18643663 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 609 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 45345 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 681 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 45180 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 26540467 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2525220 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 145175 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1675654819 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4255922 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 456905033 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 186186881 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2976415 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59600 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9064 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 763229 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5291175 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 468114 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5759289 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1486215446 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 427697474 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7356234 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 25441239 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2526766 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 145081 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1668881823 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4258646 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 454536844 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 185491805 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2961001 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59126 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7519 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 253991 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5294422 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 459505 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 5753927 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1485801812 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 427360543 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7370917 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 99535253 # number of nop insts executed -system.cpu.iew.exec_refs 599761085 # number of memory reference insts executed -system.cpu.iew.exec_branches 90544158 # Number of branches executed -system.cpu.iew.exec_stores 172063611 # Number of stores executed -system.cpu.iew.exec_rate 1.749123 # Inst execution rate -system.cpu.iew.wb_sent 1483627085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1481889704 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1175309728 # num instructions producing a value -system.cpu.iew.wb_consumers 1225337993 # num instructions consuming a value +system.cpu.iew.exec_nop 99045659 # number of nop insts executed +system.cpu.iew.exec_refs 599531836 # number of memory reference insts executed +system.cpu.iew.exec_branches 90620288 # Number of branches executed +system.cpu.iew.exec_stores 172171293 # Number of stores executed +system.cpu.iew.exec_rate 1.817200 # Inst execution rate +system.cpu.iew.wb_sent 1483493878 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1482022964 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1178273779 # num instructions producing a value +system.cpu.iew.wb_consumers 1228157747 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.744032 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.959172 # average fanout of values written-back +system.cpu.iew.wb_rate 1.812578 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.959383 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 186029259 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 179255835 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5441892 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 822794393 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.810323 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.360899 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5438120 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 791834306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.881105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.451655 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 271095175 32.95% 32.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 302645797 36.78% 69.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 45322356 5.51% 75.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 68686908 8.35% 83.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 22732084 2.76% 86.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9729610 1.18% 87.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 29628308 3.60% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10807412 1.31% 92.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 62146743 7.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 260467018 32.89% 32.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288028220 36.37% 69.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 45072234 5.69% 74.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56206737 7.10% 82.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24021941 3.03% 85.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8787658 1.11% 86.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30300633 3.83% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10698376 1.35% 91.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68251489 8.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 822794393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 791834306 # Number of insts commited each cycle system.cpu.commit.count 1489523295 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 569360986 # Number of memory references committed @@ -256,50 +256,50 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 62146743 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68251489 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2436135334 # The number of ROB reads -system.cpu.rob.rob_writes 3377694632 # The number of ROB writes -system.cpu.timesIdled 11301 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 357758 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2392297077 # The number of ROB reads +system.cpu.rob.rob_writes 3363039880 # The number of ROB writes +system.cpu.timesIdled 11286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 357787 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.604503 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.604503 # CPI: Total CPI of All Threads -system.cpu.ipc 1.654251 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.654251 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2015965671 # number of integer regfile reads -system.cpu.int_regfile_writes 1304123959 # number of integer regfile writes -system.cpu.fp_regfile_reads 16988422 # number of floating regfile reads -system.cpu.fp_regfile_writes 10452078 # number of floating regfile writes -system.cpu.misc_regfile_reads 605607850 # number of misc regfile reads +system.cpu.cpi 0.581695 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.581695 # CPI: Total CPI of All Threads +system.cpu.ipc 1.719114 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.719114 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2016058791 # number of integer regfile reads +system.cpu.int_regfile_writes 1303867666 # number of integer regfile writes +system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads +system.cpu.fp_regfile_writes 10452290 # number of floating regfile writes +system.cpu.misc_regfile_reads 605383822 # number of misc regfile reads system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes system.cpu.icache.replacements 166 # number of replacements -system.cpu.icache.tagsinuse 1030.164560 # Cycle average of tags in use -system.cpu.icache.total_refs 171980565 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1297 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 132598.739399 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 1031.400456 # Cycle average of tags in use +system.cpu.icache.total_refs 170772098 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1298 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 131565.560863 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1030.164560 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.503010 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 171980565 # number of ReadReq hits -system.cpu.icache.demand_hits 171980565 # number of demand (read+write) hits -system.cpu.icache.overall_hits 171980565 # number of overall hits -system.cpu.icache.ReadReq_misses 1801 # number of ReadReq misses -system.cpu.icache.demand_misses 1801 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 62794000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 62794000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 62794000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 171982366 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 171982366 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 171982366 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34866.185453 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34866.185453 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34866.185453 # average overall miss latency +system.cpu.icache.occ_blocks::0 1031.400456 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.503614 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 170772098 # number of ReadReq hits +system.cpu.icache.demand_hits 170772098 # number of demand (read+write) hits +system.cpu.icache.overall_hits 170772098 # number of overall hits +system.cpu.icache.ReadReq_misses 1798 # number of ReadReq misses +system.cpu.icache.demand_misses 1798 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1798 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 62741500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 62741500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 62741500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 170773896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 170773896 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 170773896 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000011 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000011 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000011 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34895.161290 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34895.161290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34895.161290 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,140 +309,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 503 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 503 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 503 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1298 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 499 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 499 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 499 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1299 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1299 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1299 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45168500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45168500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45168500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45206000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45206000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45206000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.536210 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34800.615858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 475459 # number of replacements -system.cpu.dcache.tagsinuse 4095.196777 # Cycle average of tags in use -system.cpu.dcache.total_refs 381789765 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 479555 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 796.133426 # Average number of references to valid blocks. +system.cpu.dcache.replacements 475353 # number of replacements +system.cpu.dcache.tagsinuse 4095.165283 # Cycle average of tags in use +system.cpu.dcache.total_refs 385593109 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 479449 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 804.242180 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.196777 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 216852847 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 164935599 # number of WriteReq hits +system.cpu.dcache.occ_blocks::0 4095.165283 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999796 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 220654856 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 164936934 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 381788446 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 381788446 # number of overall hits -system.cpu.dcache.ReadReq_misses 816608 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1911217 # number of WriteReq misses +system.cpu.dcache.demand_hits 385591790 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 385591790 # number of overall hits +system.cpu.dcache.ReadReq_misses 815916 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1909882 # number of WriteReq misses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 2727825 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2727825 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11966798000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 30001558232 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2725798 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2725798 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11966603000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 29861651909 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency 268000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 41968356232 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 41968356232 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 217669455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 41828254909 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 41828254909 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 221470772 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 384516271 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 384516271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.011455 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 388317588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 388317588 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.003684 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011447 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.007094 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.007094 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14654.274756 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15697.620015 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.007020 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.007020 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 14666.464440 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15635.338680 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15385.281766 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15385.281766 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency 15345.324528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15345.324528 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2071.428571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2153.846154 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 426734 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 604334 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1643943 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2248277 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2248277 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 212274 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 267274 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 426654 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 603731 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1642625 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2246356 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2246356 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 212185 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 267257 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 479548 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 479548 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 479442 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 479442 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1589212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3626989841 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1589383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3625603341 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5216201841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5216201841 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5214986841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5214986841 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000958 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001602 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001247 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001247 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7486.606933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13570.305533 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001235 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001235 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7490.555412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13565.980839 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75834 # number of replacements -system.cpu.l2cache.tagsinuse 17835.857801 # Cycle average of tags in use -system.cpu.l2cache.total_refs 464745 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91356 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.087186 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75859 # number of replacements +system.cpu.l2cache.tagsinuse 17814.801426 # Cycle average of tags in use +system.cpu.l2cache.total_refs 464590 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 91380 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.084154 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2067.900619 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15767.957182 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.063107 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.481200 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 179917 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 426734 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 206874 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 386791 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 386791 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33655 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60407 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 94062 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 94062 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1145507000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2078924500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3224431500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3224431500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 213572 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 426734 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 267281 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 480853 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 480853 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.157582 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.226006 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.195615 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.195615 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34036.755311 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34415.291274 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34279.852650 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34279.852650 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2079.678027 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15735.123399 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.063467 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.480198 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 179822 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 426654 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 206842 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 386664 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 386664 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33662 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 60422 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 94084 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 94084 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1145731000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2079178500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3224909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3224909500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 213484 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 426654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 267264 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 480748 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 480748 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.157679 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.226076 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.195703 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.195703 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34036.331769 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.951309 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34276.917435 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34276.917435 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,27 +451,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59251 # number of writebacks +system.cpu.l2cache.writebacks 59257 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33655 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60407 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 94062 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 94062 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33662 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60422 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 94084 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 94084 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1043470000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892046500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2935516500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2935516500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1043686000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2935836500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2935836500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157582 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.195615 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.195615 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.902689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31321.643187 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157679 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226076 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.195703 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.195703 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871962 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.588693 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 244f95975..a12b8078f 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/gzip +executable=/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index 03608f531..8176c7e05 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 18 2011 15:15:16 -gem5 started Aug 18 2011 15:56:00 -gem5 executing on nadc-0330 +gem5 compiled Aug 20 2011 13:24:14 +gem5 started Aug 20 2011 13:24:28 +gem5 executing on zizzer command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1064,4 +1064,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 631043541000 because target called exit() +Exiting @ tick 586755503000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index e79e605fc..5610b27f8 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.631044 # Number of seconds simulated -sim_ticks 631043541000 # Number of ticks simulated +sim_seconds 0.586756 # Number of seconds simulated +sim_ticks 586755503000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115557 # Simulator instruction rate (inst/s) -host_tick_rate 44971725 # Simulator tick rate (ticks/s) -host_mem_usage 259448 # Number of bytes of host memory used -host_seconds 14032.01 # Real time elapsed on the host +host_inst_rate 143909 # Simulator instruction rate (inst/s) +host_tick_rate 52074943 # Simulator tick rate (ticks/s) +host_mem_usage 212036 # Number of bytes of host memory used +host_seconds 11267.52 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1262087083 # number of cpu cycles simulated +system.cpu.numCycles 1173511007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 172291796 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 172291796 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7138140 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 165694672 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 164669298 # Number of BTB hits +system.cpu.BPredUnit.lookups 142841694 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142841694 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7891104 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 135940863 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 135060067 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187457062 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1372690648 # Number of instructions fetch has processed -system.cpu.fetch.Branches 172291796 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 164669298 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 395189805 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 112734719 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 580214048 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 390 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 176517375 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1196842 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1261930799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.983622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.216635 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 143543484 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1144373207 # Number of instructions fetch has processed +system.cpu.fetch.Branches 142841694 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135060067 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330625683 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 57747911 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 649508878 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 359 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 137309352 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 979465 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1173333177 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.784853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.106580 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 869789775 68.93% 68.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26036678 2.06% 70.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 17623388 1.40% 72.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17507853 1.39% 73.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23833900 1.89% 75.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16948501 1.34% 77.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37076715 2.94% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 38063595 3.02% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215050394 17.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 845712931 72.08% 72.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16031093 1.37% 73.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18099843 1.54% 74.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17610691 1.50% 76.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23355712 1.99% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16618957 1.42% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 23183901 1.98% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28217498 2.40% 84.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 184502551 15.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1261930799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136513 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.087635 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 280972137 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 498778976 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 296140618 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 86969632 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 99069436 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2448347491 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 99069436 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 329963846 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 111715541 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3471 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 317046121 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 404132384 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2409604498 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5352 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 248907784 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 129341699 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2413708682 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5838625893 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5838622529 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3364 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1173333177 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121722 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.975170 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 241132491 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 558355752 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 229474776 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 94715442 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 49654716 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2072768748 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 49654716 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 290885704 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 132416469 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3327 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 257077103 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 443295858 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2043085659 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2266 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 278274210 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 129493006 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2031275937 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4957669219 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4957665711 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3508 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 795714032 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 96 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 96 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 735209031 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 621902213 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 256079721 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 462456843 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 162376544 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2335230964 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 413281287 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 97 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 97 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 792932011 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 519352258 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 227004848 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 355033834 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 148905529 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1987362019 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1868917555 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 372085 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 713469187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1453396284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1782207350 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 181989 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 365718291 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 672335048 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1261930799 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.480998 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.347284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1173333177 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.518927 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.333963 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 328585186 26.04% 26.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 421239585 33.38% 59.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 248611798 19.70% 79.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 160686589 12.73% 91.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 61778588 4.90% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 27094790 2.15% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12009524 0.95% 99.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1648751 0.13% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 275988 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 272616502 23.23% 23.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 416904584 35.53% 58.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234897308 20.02% 78.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 156871571 13.37% 92.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 54320414 4.63% 96.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 21136145 1.80% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 14479536 1.23% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1803096 0.15% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 304021 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1261930799 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1173333177 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 173659 2.51% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6577211 95.02% 97.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 171078 2.47% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 181055 7.04% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2242910 87.15% 94.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 149595 5.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 26325646 1.41% 1.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1180659411 63.17% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 467364876 25.01% 89.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194567622 10.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 26996432 1.51% 1.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1102299326 61.85% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 458202367 25.71% 89.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194709225 10.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1868917555 # Type of FU issued -system.cpu.iq.rate 1.480815 # Inst issue rate -system.cpu.iq.fu_busy_cnt 6921948 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003704 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5007059820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3055406588 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1845403489 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1849513807 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 50 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 191278132 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1782207350 # Type of FU issued +system.cpu.iq.rate 1.518697 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2573560 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001444 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4740503284 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2353289601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1760306484 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 142 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 608 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 36 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1757784406 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 205673181 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 202860088 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 64357 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6719705 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 67893664 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 100310133 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 59834 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 216613 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 38818791 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 674 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 36961 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1385 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35852 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 99069436 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1201433 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 112801 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2335231055 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 659652 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 621902213 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 256079721 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 49654716 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1300952 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 134624 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1987362110 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 591185 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 519352258 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 227004848 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57218 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6719705 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4534206 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2790969 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7325175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1852764474 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 461769012 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 16153081 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 65366 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 216613 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4590434 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3486470 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8076904 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1768811104 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 452331737 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 13396246 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 655479520 # number of memory reference insts executed -system.cpu.iew.exec_branches 112349751 # Number of branches executed -system.cpu.iew.exec_stores 193710508 # Number of stores executed -system.cpu.iew.exec_rate 1.468016 # Inst execution rate -system.cpu.iew.wb_sent 1850700108 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1845403509 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1443346270 # num instructions producing a value -system.cpu.iew.wb_consumers 2115960944 # num instructions consuming a value +system.cpu.iew.exec_refs 646217865 # number of memory reference insts executed +system.cpu.iew.exec_branches 112172746 # Number of branches executed +system.cpu.iew.exec_stores 193886128 # Number of stores executed +system.cpu.iew.exec_rate 1.507281 # Inst execution rate +system.cpu.iew.wb_sent 1766741886 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1760306520 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1336435928 # num instructions producing a value +system.cpu.iew.wb_consumers 2002913192 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.462184 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682123 # average fanout of values written-back +system.cpu.iew.wb_rate 1.500034 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667246 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 713749948 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 365887065 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7138191 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1162861363 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.394400 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.690304 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7891152 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1123678461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.443023 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.662640 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 395572650 34.02% 34.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 431612406 37.12% 71.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 98230430 8.45% 79.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 129131818 11.10% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30975376 2.66% 93.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25883779 2.23% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22467188 1.93% 97.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 13999993 1.20% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14987723 1.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 347480674 30.92% 30.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 438655867 39.04% 69.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 94938828 8.45% 78.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 133745830 11.90% 90.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36833685 3.28% 93.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26175862 2.33% 95.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22548594 2.01% 97.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8175613 0.73% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15123508 1.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1162861363 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1123678461 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -255,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14987723 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15123508 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3483117570 # The number of ROB reads -system.cpu.rob.rob_writes 4770120987 # The number of ROB writes -system.cpu.timesIdled 44517 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 156284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3095936000 # The number of ROB reads +system.cpu.rob.rob_writes 4024437562 # The number of ROB writes +system.cpu.timesIdled 44153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 177830 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.778348 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.778348 # CPI: Total CPI of All Threads -system.cpu.ipc 1.284772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.284772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289423155 # number of integer regfile reads -system.cpu.int_regfile_writes 1840387955 # number of integer regfile writes -system.cpu.fp_regfile_reads 20 # number of floating regfile reads -system.cpu.misc_regfile_reads 943704220 # number of misc regfile reads -system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 813.354682 # Cycle average of tags in use -system.cpu.icache.total_refs 176516095 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 197445.296421 # Average number of references to valid blocks. +system.cpu.cpi 0.723722 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.723722 # CPI: Total CPI of All Threads +system.cpu.ipc 1.381746 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.381746 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3273654764 # number of integer regfile reads +system.cpu.int_regfile_writes 1756473314 # number of integer regfile writes +system.cpu.fp_regfile_reads 36 # number of floating regfile reads +system.cpu.misc_regfile_reads 909253494 # number of misc regfile reads +system.cpu.icache.replacements 16 # number of replacements +system.cpu.icache.tagsinuse 813.268656 # Cycle average of tags in use +system.cpu.icache.total_refs 137308116 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 900 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 152564.573333 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 813.354682 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.397146 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 176516138 # number of ReadReq hits -system.cpu.icache.demand_hits 176516138 # number of demand (read+write) hits -system.cpu.icache.overall_hits 176516138 # number of overall hits -system.cpu.icache.ReadReq_misses 1237 # number of ReadReq misses -system.cpu.icache.demand_misses 1237 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1237 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 43406000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 43406000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 43406000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 176517375 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 176517375 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 176517375 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35089.733226 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35089.733226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35089.733226 # average overall miss latency +system.cpu.icache.occ_blocks::0 813.268656 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.397104 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 137308116 # number of ReadReq hits +system.cpu.icache.demand_hits 137308116 # number of demand (read+write) hits +system.cpu.icache.overall_hits 137308116 # number of overall hits +system.cpu.icache.ReadReq_misses 1236 # number of ReadReq misses +system.cpu.icache.demand_misses 1236 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1236 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 43480000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 43480000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 43480000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 137309352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 137309352 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 137309352 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35177.993528 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35177.993528 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35177.993528 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -306,167 +306,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 339 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 339 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 898 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 898 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 898 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 336 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 336 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 900 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 900 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 900 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 31587000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 31587000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 31587000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 31792500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 31792500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 31792500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35174.832962 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35174.832962 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35174.832962 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35325 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35325 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35325 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459230 # number of replacements -system.cpu.dcache.tagsinuse 4094.984798 # Cycle average of tags in use -system.cpu.dcache.total_refs 457142531 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463326 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 986.654172 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317737000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.984798 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999752 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 270249416 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 186893112 # number of WriteReq hits -system.cpu.dcache.demand_hits 457142528 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 457142528 # number of overall hits -system.cpu.dcache.ReadReq_misses 217407 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1292945 # number of WriteReq misses -system.cpu.dcache.demand_misses 1510352 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1510352 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2208510500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25332209498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 27540719998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 27540719998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 270466823 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 459082 # number of replacements +system.cpu.dcache.tagsinuse 4094.908409 # Cycle average of tags in use +system.cpu.dcache.total_refs 433296852 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463178 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 935.486685 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317735000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.908409 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999733 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 246417961 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186878891 # number of WriteReq hits +system.cpu.dcache.demand_hits 433296852 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 433296852 # number of overall hits +system.cpu.dcache.ReadReq_misses 217222 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1307166 # number of WriteReq misses +system.cpu.dcache.demand_misses 1524388 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1524388 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2206460500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25191688497 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 27398148997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 27398148997 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 246635183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 458652880 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 458652880 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000804 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006871 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.003293 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003293 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10158.414862 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19592.642764 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18234.636693 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18234.636693 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1882500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 494592500 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 434821240 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 434821240 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000881 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.003506 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.003506 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10157.629062 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19271.988789 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 17973.212199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 17973.212199 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1884500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 490158000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 34873 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3905.601660 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14182.677143 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 33499 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3909.751037 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14632.018866 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213604 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249576 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463180 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463180 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1535603000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2500577500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4036180500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4036180500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1533784000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2518332500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4052116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4052116500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000791 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001010 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001010 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7181.587747 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10022.153865 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8711.243606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8711.243606 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001065 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001065 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7180.502238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10090.443392 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73611 # number of replacements -system.cpu.l2cache.tagsinuse 18032.065292 # Cycle average of tags in use -system.cpu.l2cache.total_refs 453266 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89232 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.079635 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73626 # number of replacements +system.cpu.l2cache.tagsinuse 17961.057219 # Cycle average of tags in use +system.cpu.l2cache.total_refs 452680 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89247 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.072215 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1960.203068 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16071.862223 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.059821 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.490474 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181561 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 410188 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 190780 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 372341 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 372341 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33157 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 58724 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91881 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91881 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1130411500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2017247500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3147659000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3147659000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214718 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 410188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249504 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464222 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464222 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154421 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235363 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197925 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197925 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34092.695358 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34351.329950 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34257.996757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34257.996757 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 204000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1976.377276 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15984.679942 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.060314 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487814 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181326 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 410010 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 190857 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 372183 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 372183 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33178 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58719 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91897 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91897 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1131489500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2019003500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3150493000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3150493000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214504 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 410010 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249576 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464080 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464080 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154673 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235275 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.198020 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.198020 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34103.607812 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34384.160153 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34282.871040 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34282.871040 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 202000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 121 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1685.950413 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1655.737705 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58498 # number of writebacks +system.cpu.l2cache.writebacks 58507 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33157 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58724 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91881 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91881 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33178 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58719 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91897 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91897 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1028041500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829105500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2857147000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2857147000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1028691000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828336500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2857027500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2857027500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235363 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197925 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197925 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.262840 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31147.495062 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31096.167869 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31096.167869 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154673 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235275 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.198020 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.198020 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.214299 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.051040 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |