diff options
Diffstat (limited to 'tests/long/00.gzip/ref')
8 files changed, 64 insertions, 64 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 10e34acb3..a72d72f62 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:05:54 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:02:50 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index bb82434d0..0e211038a 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 385051 # Simulator instruction rate (inst/s) -host_mem_usage 204468 # Number of bytes of host memory used -host_seconds 1468.77 # Real time elapsed on the host -host_tick_rate 110529153 # Simulator tick rate (ticks/s) +host_inst_rate 235652 # Simulator instruction rate (inst/s) +host_mem_usage 207744 # Number of bytes of host memory used +host_seconds 2399.95 # Real time elapsed on the host +host_tick_rate 67644016 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162342 # Number of seconds simulated @@ -254,16 +254,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10009719 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 24101 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6020 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11448147 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3134413 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 10009719 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 24101 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 6020 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 11448147 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 3134413 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index facf2b9b0..408898e50 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 12:47:12 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:06:31 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 5fb65989e..cd3ca8de5 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 283332 # Simulator instruction rate (inst/s) -host_mem_usage 214996 # Number of bytes of host memory used -host_seconds 2125.99 # Real time elapsed on the host -host_tick_rate 92433779 # Simulator tick rate (ticks/s) +host_inst_rate 169360 # Simulator instruction rate (inst/s) +host_mem_usage 217476 # Number of bytes of host memory used +host_seconds 3556.69 # Real time elapsed on the host +host_tick_rate 55251704 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 602359865 # Number of instructions simulated sim_seconds 0.196513 # Number of seconds simulated @@ -265,16 +265,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 3721 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 12871984 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 65726 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 25082678 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 611520 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15892 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 27153747 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 11966835 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 25082678 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 611520 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 15892 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 27153747 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 11966835 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 9d435e3a3..750396309 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:20:08 +M5 compiled Apr 21 2011 13:27:10 +M5 started Apr 21 2011 13:30:00 M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 04c8a25b6..9d595253b 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 280029 # Simulator instruction rate (inst/s) -host_mem_usage 206320 # Number of bytes of host memory used -host_seconds 5019.49 # Real time elapsed on the host -host_tick_rate 116031336 # Simulator tick rate (ticks/s) +host_inst_rate 154343 # Simulator instruction rate (inst/s) +host_mem_usage 212152 # Number of bytes of host memory used +host_seconds 9107.03 # Real time elapsed on the host +host_tick_rate 63952564 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.582418 # Number of seconds simulated @@ -243,16 +243,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 8462 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 27885594 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 128708 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 129748862 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 460365 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 237 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 58644458 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 20174020 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 129748862 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 460365 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 237 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 58644458 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 20174020 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 670427 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index f0ad86715..fc45f8a25 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:31:00 +M5 compiled Apr 21 2011 13:30:37 +M5 started Apr 21 2011 13:30:43 M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 99a6b6318..a21571816 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 229365 # Simulator instruction rate (inst/s) -host_mem_usage 211952 # Number of bytes of host memory used -host_seconds 7069.49 # Real time elapsed on the host -host_tick_rate 106242349 # Simulator tick rate (ticks/s) +host_inst_rate 131052 # Simulator instruction rate (inst/s) +host_mem_usage 215332 # Number of bytes of host memory used +host_seconds 12372.92 # Real time elapsed on the host +host_tick_rate 60703496 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated sim_seconds 0.751079 # Number of seconds simulated @@ -232,16 +232,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 99378480 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 111986 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 119484333 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6399400 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 47 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 196809249 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 62612798 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 119484333 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 6399400 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 196809249 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 62612798 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly |