diff options
Diffstat (limited to 'tests/long/00.gzip/ref')
24 files changed, 127 insertions, 84 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 96f36a5ca..474c2633d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 8697d1b4d..223344a8e 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:50:56 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:02:05 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index ec3407f13..b56c75dd6 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 305062 # Simulator instruction rate (inst/s) -host_mem_usage 190836 # Number of bytes of host memory used -host_seconds 1853.89 # Real time elapsed on the host -host_tick_rate 90122857 # Simulator tick rate (ticks/s) +host_inst_rate 207071 # Simulator instruction rate (inst/s) +host_mem_usage 192708 # Number of bytes of host memory used +host_seconds 2731.20 # Real time elapsed on the host +host_tick_rate 61173967 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.167078 # Number of seconds simulated @@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses 553555 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999561 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.203417 # Average occupied blocks per context system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency @@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses 902 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.375881 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 769.803945 # Average occupied blocks per context system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency @@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses 292443 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.051040 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.447409 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1672.465668 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14660.696789 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index af1fb07c3..d1818975e 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout index 760b4567a..d257950b6 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:08 -M5 executing on zizzer +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:36:02 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index ecc08006d..11a5d6497 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3845310 # Simulator instruction rate (inst/s) -host_mem_usage 195720 # Number of bytes of host memory used -host_seconds 156.52 # Real time elapsed on the host -host_tick_rate 1922667398 # Simulator tick rate (ticks/s) +host_inst_rate 1810362 # Simulator instruction rate (inst/s) +host_mem_usage 184036 # Number of bytes of host memory used +host_seconds 332.45 # Real time elapsed on the host +host_tick_rate 905187706 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 014dd0eae..812afa499 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 6de92788c..c1023446a 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:05:42 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:27:06 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index dfa3f12e0..53f0d7951 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2876228 # Simulator instruction rate (inst/s) -host_mem_usage 205052 # Number of bytes of host memory used -host_seconds 209.25 # Real time elapsed on the host -host_tick_rate 3718015194 # Simulator tick rate (ticks/s) +host_inst_rate 1555765 # Simulator instruction rate (inst/s) +host_mem_usage 191800 # Number of bytes of host memory used +host_seconds 386.86 # Real time elapsed on the host +host_tick_rate 2011092592 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.778004 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 530123 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999559 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.195523 # Average occupied blocks per context system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 795 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.328723 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 673.225223 # Average occupied blocks per context system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses 288954 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.050771 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.447994 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1663.663316 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14679.879055 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index b155134f9..4a852e5ff 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 80363a0dc..23f626d38 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:07:18 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 12:13:14 -M5 executing on maize +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:11:32 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 6edc71271..e06d74489 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146091 # Simulator instruction rate (inst/s) -host_mem_usage 192556 # Number of bytes of host memory used -host_seconds 9621.55 # Real time elapsed on the host -host_tick_rate 114603106 # Simulator tick rate (ticks/s) +host_inst_rate 117151 # Simulator instruction rate (inst/s) +host_mem_usage 194316 # Number of bytes of host memory used +host_seconds 11998.32 # Real time elapsed on the host +host_tick_rate 91901100 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618365 # Number of instructions simulated sim_seconds 1.102659 # Number of seconds simulated @@ -103,6 +103,8 @@ system.cpu.dcache.demand_mshr_misses 600222 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999897 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.579742 # Average occupied blocks per context system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 30916.284897 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency @@ -190,6 +192,8 @@ system.cpu.icache.demand_mshr_misses 1379 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.516598 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1057.993144 # Average occupied blocks per context system.cpu.icache.overall_accesses 354588619 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency @@ -364,6 +368,10 @@ system.cpu.l2cache.demand_mshr_misses 314075 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.055938 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.444640 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1832.969770 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14569.950583 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34273.636870 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 92041a7ce..724bab032 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index c6ea04920..c99734c27 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:04:58 -M5 executing on zizzer +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:19:07 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index 99ed606e5..d04149323 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2585505 # Simulator instruction rate (inst/s) -host_mem_usage 197792 # Number of bytes of host memory used -host_seconds 576.11 # Real time elapsed on the host -host_tick_rate 1292756549 # Simulator tick rate (ticks/s) +host_inst_rate 1748575 # Simulator instruction rate (inst/s) +host_mem_usage 185740 # Number of bytes of host memory used +host_seconds 851.85 # Real time elapsed on the host +host_tick_rate 874289976 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 0.744764 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 2b302db2e..4f8cbe2e9 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 224bbd08c..be22dcc27 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:47 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:25:44 -M5 executing on maize +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:27:10 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 72665606e..89a25e955 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2042056 # Simulator instruction rate (inst/s) -host_mem_usage 207148 # Number of bytes of host memory used -host_seconds 729.42 # Real time elapsed on the host -host_tick_rate 2846083906 # Simulator tick rate (ticks/s) +host_inst_rate 933241 # Simulator instruction rate (inst/s) +host_mem_usage 193388 # Number of bytes of host memory used +host_seconds 1596.08 # Real time elapsed on the host +host_tick_rate 1300690172 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.076001 # Number of seconds simulated @@ -60,6 +60,8 @@ system.cpu.dcache.demand_mshr_misses 513081 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999812 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.229973 # Average occupied blocks per context system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency @@ -113,6 +115,8 @@ system.cpu.icache.demand_mshr_misses 1107 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.442585 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 906.413760 # Average occupied blocks per context system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency @@ -187,6 +191,10 @@ system.cpu.l2cache.demand_mshr_misses 293479 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.052187 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.447022 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1710.054315 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14648.032371 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 8edc68d8c..8ce850818 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 4a4332de9..dd9141c9e 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:09:46 -M5 executing on tater +M5 compiled Feb 25 2010 03:41:05 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:41:09 +M5 executing on SC2B0619 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index f1a9425ca..eeabe51c0 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1432576 # Simulator instruction rate (inst/s) -host_mem_usage 198272 # Number of bytes of host memory used -host_seconds 1130.39 # Real time elapsed on the host -host_tick_rate 851856908 # Simulator tick rate (ticks/s) +host_inst_rate 1572419 # Simulator instruction rate (inst/s) +host_mem_usage 188984 # Number of bytes of host memory used +host_seconds 1029.86 # Real time elapsed on the host +host_tick_rate 935012313 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619366736 # Number of instructions simulated sim_seconds 0.962929 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 0c81e9129..c67ff9af1 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -45,6 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -79,6 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -113,6 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -154,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 8936a6094..68f564509 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 8 2009 16:16:58 -M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff -M5 started Nov 8 2009 16:32:22 -M5 executing on maize +M5 compiled Feb 25 2010 03:41:05 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:47:37 +M5 executing on SC2B0619 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 60806dc72..59d079222 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1181561 # Simulator instruction rate (inst/s) -host_mem_usage 194380 # Number of bytes of host memory used -host_seconds 1370.53 # Real time elapsed on the host -host_tick_rate 1324103876 # Simulator tick rate (ticks/s) +host_inst_rate 992380 # Simulator instruction rate (inst/s) +host_mem_usage 196544 # Number of bytes of host memory used +host_seconds 1631.80 # Real time elapsed on the host +host_tick_rate 1112100106 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619366736 # Number of instructions simulated sim_seconds 1.814727 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 506760 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.901154 # Average occupied blocks per context system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42325.964954 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39325.964954 # average overall mshr miss latency @@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.322346 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 660.164909 # Average occupied blocks per context system.cpu.icache.overall_accesses 1186516703 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses 277801 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.052737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.452189 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1728.087970 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14817.313734 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 442788 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |